EVAL-AD7450ASDZ Analog Devices, EVAL-AD7450ASDZ Datasheet - Page 24
Manufacturer Part Number
Data Conversion IC Development Tools EVALUATION BOARD I.C.
Specifications of EVAL-AD7450ASDZ
Tool Is For Evaluation Of
Operating Supply Voltage
2.7 V to 5.25 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Factory Pack Quantity
If CS is brought high before the 10th falling edge of SCLK, the
AD7440/AD7450A again goes back into power-down. This
avoids accidental power-up due to glitches on the CS line or an
inadvertent burst of eight SCLK cycles while CS is low. So
although the device may begin to power up on the falling edge
of CS , it again powers down on the rising edge of CS as long as
it occurs before the 10th SCLK falling edge.
The power-up time of the AD7440/AD7450A is typically 1 μs,
which means that with any frequency of SCLK up to 18 MHz,
one dummy cycle is always sufficient to allow the device to
power up. Once the dummy cycle is complete, the ADC is fully
powered up and the input signal is acquired properly. The quiet
bus goes back into three-state after the dummy conversion to
the next falling edge of CS .
When running at the maximum throughput rate of 1 MSPS, the
AD7440/AD7450A power up and acquire a signal within
±0.5 LSB in one dummy cycle, 1 μs. When powering up from
the power-down mode with a dummy cycle, as in Figure 43, the
track-and-hold, which was in hold mode while the part was
powered down, returns to track mode after the first SCLK edge
the part receives after the falling edge of CS . This is shown as
Point A in Figure 43.
Although at any SCLK frequency one dummy cycle is sufficient
to power up the device and acquire V
full dummy cycle of 16 SCLKs must always elapse to power up
the device and acquire V
the device and acquire the input signal.
For example, if a 5 MHz SCLK frequency was applied to the
ADC, the cycle time would be 3.2 μs (1/(5 MHz) × 16). In one
dummy cycle, 3.2 μs, the part would be powered up and V
acquired fully. However, after 1 μs with a 5 MHz SCLK, only
five SCLK cycles would have elapsed. At this stage, the ADC
would be fully powered up and the signal acquired. So in this
case, the CS can be brought high after the 10th SCLK falling
edge and brought low again after a time, t
When power supplies are first applied to the device, the ADC
may power up in either power-down mode or normal mode.
Because of this, it is best to allow a dummy cycle to elapse to
ensure the part is fully powered up before attempting a valid
conversion. Likewise, if the user wants the part to power up in
power-down mode, the dummy cycle may be used to ensure the
device is in power-down by executing a cycle such as the one
shown in Figure 42.
, must still be allowed from the point at which the
fully; 1 μs is sufficient to power up
, it does not mean that a
, to initiate the
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Once supplies are applied to the AD7440/AD7450A, the power-
up time is the same as that when powering up from power-
down mode. It takes about 1 μs to power up fully if the part
powers up in normal mode. It is not necessary to wait 1 μs
before executing a dummy cycle to ensure the desired mode of
operation. Instead, the dummy cycle can occur directly after
power is supplied to the ADC. If the first valid conversion is
then performed directly after the dummy conversion, ensure
that adequate acquisition time has been allowed.
As mentioned earlier, when powering up from the power-down
mode, the part returns to track mode upon the first SCLK edge
applied after the falling edge of CS . However, when the ADC
powers up initially after supplies are applied, the track-and-hold
is already in track mode. Assuming the user has the facility to
monitor the ADC supply current, this means the ADC powers
up in the desired mode of operation, and thus a dummy cycle is
not required to change mode. A dummy cycle is therefore not
required to place the track-and-hold into track mode.
POWER VS. THROUGHPUT RATE
By using the power-down mode on the AD7440/AD7450A
when not converting, the average power consumption of the
ADC decreases at lower throughput rates. Figure 44 shows how,
as the throughput rate is reduced, the device remains in its
power-down state longer and the average power consumption is
reduced accordingly for both 5 V and 3 V power supplies.
For example, if the AD7440/AD7450A are operated in
continuous sampling mode with a throughput rate of 100 kSPS
and an SCLK of 18 MHz, and the device is placed in power-
down mode between conversions, the power consumption is
calculated as follows:
Power Dissipation during Normal Operation = 9.25 mW max
If the power-up time is one dummy cycle (1 μs), and the
remaining conversion time is another cycle (1 μs), the
AD7440/AD7450A can be said to dissipate 9.25 mW for 2 μs
during each conversion cycle.
If the throughput rate = 100 kSPS, the cycle time = 10 μs and
the average power dissipated during each cycle is
(2/10) × 9.25 mW = 1.85 mW.
For the same scenario, if V
during normal operation is 4 mW max.
The AD7440/AD7450A can now be said to dissipate 4 mW for
This figure assumes a very short time to enter power-down mode. This
increases as the burst of clocks used to enter this mode is increased.
during each conversion cycle.
= 5 V)
= 3 V, the power dissipation