EVAL-AD7450ASDZ

Manufacturer Part NumberEVAL-AD7450ASDZ
DescriptionData Conversion IC Development Tools EVALUATION BOARD I.C.
ManufacturerAnalog Devices
TypeADC
SeriesAD7450A
EVAL-AD7450ASDZ datasheet
 

Specifications of EVAL-AD7450ASDZ

RohsyesProductEvaluation Boards
Tool Is For Evaluation OfAD7450AInterface TypeSerial
Operating Supply Voltage2.7 V to 5.25 VMaximum Operating Temperature+ 85 C
Minimum Operating Temperature- 40 CFactory Pack Quantity1
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TIMING SPECIFICATIONS
Guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
1.6 V. See Figure 2, Figure 3, and the Serial Interface section.
Table 3. V
= 2.7 V to 3.6 V, f
= 18 MHz, f
DD
SCLK
1
V
= 2.5 V; V
= V
; T
= T
to T
REF
CM
REF
A
MIN
Parameter
Limit at T
, T
MIN
MAX
2
f
10
SCLK
18
t
16 × t
CONVERT
SCLK
888
t
60
QUIET
t
10
1
t
10
2
3
t
20
3
t
3
40
4
t
0.4 t
5
SCLK
t
0.4 t
6
SCLK
t
10
7
4
t
10
8
35
5
t
1
POWER-UP
1
Common-mode voltage.
2
Mark/space ratio for the SCLK input is 40/60 to 60/40.
3
Measured with the load circuit of Figure 4 and defined as the time required for the output to cross 0.8 V or 2.4 V with V
4
t
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 4. The measured number is then extrapolated
8
back to remove the effects of charging or discharging the 25 pF capacitor. This means that the time, t
time of the part and is independent of the bus loading.
5
See Power-Up Time section.
CS
t
2
1
2
SCLK
t
3
0
0
SDATA
4 LEADING ZEROS
CS
t
2
1
2
SCLK
t
3
0
0
SDATA
4 LEADING ZEROS
= 1 MSPS, V
= 2.0 V; V
S
REF
DD
, unless otherwise noted.
MAX
Unit
Description
kHz min
MHz max
t
= 1/f
SCLK
SCLK
ns max
Minimum quiet time between the end of a serial read and the next falling edge of CS
ns min
ns min
Minimum CS pulse width
CS falling edge to SCLK falling edge setup time
ns min
Delay from CS falling edge until SDATA three-state disabled
ns max
ns max
Data access time after SCLK falling edge
ns min
SCLK high pulse width
ns min
SCLK low pulse width
ns min
SCLK edge to data valid hold time
ns min
SCLK falling edge to SDATA three-state enabled
ns max
SCLK falling edge to SDATA three-state enabled
μs max
Power-up time from full power-down
t
CONVERT
t
B
5
3
4
5
13
t
7
t
4
0
0
DB11
DB10
Figure 2. AD7450A Serial Interface Timing Diagram
t
CONVERT
t
B
5
3
4
5
13
t
7
t
4
0
0
DB9
DB8
Figure 3. AD7440 Serial Interface Timing Diagram
Rev. C | Page 7 of 28
AD7440/AD7450A
) and timed from a voltage level of
DD
= 4.75 V to 5.25 V, f
= 18 MHz, f
= 1 MSPS,
SCLK
S
= 5 V or 0.4 V or 2.0 V for V
DD
, quoted in the Timing Specifications is the true bus relinquish
8
t
1
14
15
16
t
t
6
8
t
QUIET
DB2
DB1
DB0
THREE-STATE
t
1
14
15
16
t
t
6
8
t
QUIET
DB0
0
0
2 TRAILING ZEROS THREE-STATE
= 3 V.
DD