AD6643-250EBZ Analog Devices, AD6643-250EBZ Datasheet - Page 25

• Manufacturer Part Number: AD6643-250EBZ
• Description: Data Conversion IC Development Tools 11 Bit Dual IF Diversity 3G Receiver
• Manufacturer: Analog Devices
• Type: ADCr
• Series: AD6643r

Specifications of AD6643-250EBZ

• Rohs: yes
• Product: Evaluation Boards
• Tool Is For Evaluation Of: AD6643-250
• Interface Type: SPI, USB
• Operating Supply Voltage: 6 V
• Description/function: 250 MSPs per channel dual IF receiver
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Current: 2 A
• Factory Pack Quantity: 1
• For Use With: HSC-ADC-EVALCZ

Data Sheet
power-down, the output drivers are placed in a high impedance
state. Asserting the PDWN pin low returns the AD6643 to its
normal operating mode. Note that PDWN is referenced to the
digital output driver supply (DRVDD) and should not exceed
that supply voltage.
Low power dissipation in power-down mode is achieved by
shutting down the reference, reference buffer, biasing networks,
and clock. Internal capacitors are discharged when entering power-
down mode and then must be recharged when returning to normal
operation. As a result, wake-up time is related to the time spent
in power-down mode, and shorter power-down cycles result in
proportionally shorter wake-up times.
When using the SPI port interface, the user can place the ADC
in power-down mode or standby mode. Standby mode allows
the user to keep the internal reference circuitry powered when
faster wake-up times are required. See the Memory Map Register
Description section and the
to High Speed ADCs via SPI, available at
additional details.
DIGITAL OUTPUTS
The AD6643 output drivers can be configured for either ANSI
LVDS or reduced drive LVDS using a 1.8 V DRVDD supply.
As detailed in the
Speed ADCs via SPI, the data format can be selected for offset
binary, twos complement, or gray code when using the SPI
control.
Digital Output Enable Function (OEB)
The AD6643 has a flexible three-state ability for the digital
output pins. The three-state mode is enabled using the OEB pin
or through the SPI interface. If the OEB pin is low, the output
data drivers are enabled. If the OEB pin is high, the output data
drivers are placed in a high impedance state. This OEB function
Table 11. Output Data Format
Input (V)
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
AN-877
VIN+ − VIN−,
Input Span = 1.75 V p-p (V)
Less than −0.875
−0.875
0
+ 0.875
Greater than + 0.875
Application Note, Interfacing to High
AN-877
Application Note, Interfacing
www.analog.com
Offset Binary Output Mode
000 0000 0000
000 0000 0000
100 0000 0000
111 1111 1111
111 1111 1111
for
Rev. C | Page 25 of 40
is not intended for rapid access to the data bus. Note that OEB
is referenced to the digital output driver supply (DRVDD) and
should not exceed that supply voltage.
When using the SPI interface, the data outputs of each channel
can be independently three-stated by using the output disable
bar bit (Bit 4) in Register 0x14. Because the output data is inter-
leaved, if only one of the two channels is disabled, the data from
the remaining channel is repeated in both the rising and falling
output clock cycles.
Timing
The AD6643 provides latched data with a pipeline delay of 10 input
sample clock cycles (13 input sample clock cycles when NSR is
enabled). Data outputs are available one propagation delay (t
after the rising edge of the clock signal.
To reduce transients within the AD6643, minimize the length of
the output data lines and loads that are placed on them. These
transients can degrade converter dynamic performance.
The lowest typical conversion rate of the AD6643 is 40 MSPS. At
clock rates below 40 MSPS, dynamic performance can degrade.
Data Clock Output (DCO)
The AD6643 also provides data clock output (DCO) intended for
capturing the data in an external register. Figure 2 shows a
graphical timing diagram of the AD6643 output modes.
ADC OVERRANGE (OR)
The ADC overrange indicator is asserted when an overrange is
detected on the input of the ADC. The overrange condition is
determined at the output of the ADC pipeline and, therefore, is
subject to a latency of 10 ADC clock cycles (13 ADC clock cycles
with NSR enabled). An overrange at the input is indicated by this
bit 10 clock cycles after it occurs (13 clock cycles with NSR
enabled).
Twos Complement Mode (Default)
100 0000 0000
100 0000 0000
000 0000 0000
011 1111 1111
011 1111 1111
AD6643
OR
1
0
0
0
1
PD
)