MAX1276EVKIT Maxim Integrated, MAX1276EVKIT Datasheet - Page 13

• Manufacturer Part Number: MAX1276EVKIT
• Description: Data Conversion IC Development Tools Evaluation Kit/Evaluation System for the MAX1070/71/72/75#79/MAX1224/25/MAX1274#79
• Manufacturer: Maxim Integrated
• Series: MAX1276, MAX1278r

Specifications of MAX1276EVKIT

• Interface Type: QSPI, Serial (SPI, Microwire)

with their ground nodes connected to the RGND pin.
The traces should be made as wide as possible to min-
imize parasitics and the reference capacitors should be
mounted as close to the ADC as possible.
At least 4.7µF of capacitance is required for internal
buffer stability. A small-value high-frequency bypass
capacitor is also recommended.
The MAX1276 is sensitive to excessive loading on the
DOUT pin. In the EV kit, a high-speed low-power AND
gate (U4, a SN74LVC1G08) buffers the MAX1276’s
DOUT from excessive loading. It is recommended that
the buffered output (available on header P1 pin 7 or the
DOUT pad loop) be used when connecting logic ana-
lyzers or other external loads. Direct connection to the
digital output of the test device can be accessed
through P1 pin 5 for evaluating output drive strength
and timing characteristics. Note: A 100Ω series isola-
tion resistor and the load of the U4 input remains in the
circuit when evaluating the direct connection.
Achieving peak performance of any high-speed data
converter requires careful attention to component
placement and signal integrity on the PC board. It is
Figure 6. Valid Bipolar Waveform Examples
Table 6. Reference Configurations
Internal
External (VREF)
External (VDD)
TEST-DEVICE
REFERENCE
MAX1276 Evaluation Kit/Evaluation System
VREF
______________________________________________________________________________________
AIN-
AIN+
VREF-PAD
FUNCTION
Digital Output Buffering
Output
BSP: BIPOLAR SE AC+
Input
N/C
PC-Board Layout
JU3
1-2
1-2
2-3
AIN+
AIN-
BSM: BIPOLAR SE AC-
suggested that the user duplicate the layout of the
MAX1276 EV kit board to the maximum possible extent
allowed by their application.
Near the ADC, proper star-grounding techniques pro-
vide maximum performance. Local connections to GND
and RGND pins initiate at the exposed paddle of the
ADC and a dedicated ground return trace is routed
directly to the AGND pad.
For high-speed operational amplifiers (U2 and U3),
stray capacitance on the input pins can adversely
affect the performance. Components connected to the
inputs of these buffers are located as close as possible
to the input and the ground plane is removed below
these pins to reduce stray capacitance.
Two separate ground planes exist for the analog and
digital components. Connections to the two planes are
indicated by different symbols on the schematic.
Ground connections for the digital signal connections
(and the digital buffer U4) are tied to the digital ground
plane. All others are tied to the analog ground. A look
at the second layer
planes located on an interior layer.
The ground planes are shorted as close to the part as
possible through a 0Ω resistor (short) in location FB2.
This method has proven to provide the best noise
rejection and dynamic performance. In practice, some
users prefer isolating the ground planes through a
resistor or ferrite bead.
VREF / 2
AIN+
AIN-
BD: BIPOLAR DIFFERENTIAL
(Figure
13) reveals the two ground
13