MT48LC8M8A2P-75:G Micron Technology Inc, MT48LC8M8A2P-75:G Datasheet - Page 12

• Manufacturer Part Number: MT48LC8M8A2P-75:G
• Description: IC SDRAM 64MBIT 133MHZ 54TSOP
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC8M8A2P-75:G

• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 64M (8M x 8)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 54-TSOP II
• Organization: 8Mx8
• Density: 64Mb
• Address Bus: 14b
• Access Time (max): 6/5.4ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 140mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 4:
Functional Description
Initialization
PDF: 09005aef80725c0b/Source: 09005aef806fc13c
64MSDRAM_2.fm - Rev. N 12/08 EN
3, 9, 43, 49 A7, B3, C7,
Numbers
TSOP Pin
28, 41, 54
6, 12, 46,
1, 14, 27
36
52
A3, B7, C3,
Pin/Ball Descriptions
Numbers
A9, E7, J9
A1, E3, J1
VFBGA
Ball
G1
D3
D7
Symbol
In general, the 64Mb SDRAM (4 Meg x 4 x 4 banks, 2 Meg x 8 x 4 banks, and 1 Meg x 16 x 4
banks) is a quad-bank DRAM that operates at 3.3V and includes a synchronous interface
(all signals are registered on the positive edge of the clock signal, CLK). Each of the x4’s
16,777,216-bit banks is organized as 4,096 rows by 1,024 columns by 4 bits. Each of the
x8’s 16,777,216-bit banks is organized as 4,096 rows by 512 columns by 8 bits. Each of the
x16’s 16,777,216-bit banks is organized as 4,096 rows by 256 columns by 16 bits.
Read and write accesses to the SDRAM are burst oriented; accesses start at a selected
location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE command which is then
followed by a READ or WRITE command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to be accessed (BA0 and BA1
select the bank, A0–A11 select the row). The address bits (x4: A0–A9; x8: A0–A8; x16:
A0–A7) registered coincident with the READ or WRITE command are used to select the
starting column location for the burst access.
Prior to normal operation, the SDRAM must be initialized. The following sections
provide detailed information covering device initialization, register definition,
command descriptions and device operation.
SDRAMs must be powered up and initialized in a predefined manner. Operational
procedures other than those specified may result in undefined operation. After power is
applied to V
defined as a signal cycling within timing constraints specified for the clock pin), the
SDRAM requires a 100µs delay prior to issuing any command other than a COMMAND
INHIBIT or NOP . Starting at some point during this 100µs period and continuing at least
through the end of this period, COMMAND INHIBIT or NOP commands must be
applied.
Once the 100µs delay has been satisfied with at least one COMMAND INHIBIT or NOP
command having been applied, a PRECHARGE command should be applied. All banks
must then be precharged, thereby placing the device in the all banks idle state.
After the idle state, at least two AUTO REFRESH cycles must be performed. After the
AUTO REFRESH cycles are complete, the SDRAM is ready for mode register program-
ming. Because the mode register will power up in an unknown state, it must be loaded
prior to applying any operational command. If desired, the two AUTO REFRESH
commands can be issued after the LOAD MODE REGISTER command.
V
V
V
V
NC
DD
SS
DD
SS
Q
Q
DD
Supply
Supply
Supply
Supply
Type
–
and V
DD
No connect: May be used as address inputs (A12) on the 256Mb and
512Mb devices.
DQ power: Isolated DQ power on the die for improved noise
immunity.
DQ ground: Isolated DQ ground on the die for improved noise
immunity.
Power supply: +3.3V ±0.3V.
Ground.
Q (simultaneously) and the clock is stable (stable clock is
12
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Description
64Mb: x4, x8, x16 SDRAM
Functional Description
©2000 Micron Technology, Inc. All rights reserved.