MT48LC8M8A2P-75:G Micron Technology Inc, MT48LC8M8A2P-75:G Datasheet - Page 2

• Manufacturer Part Number: MT48LC8M8A2P-75:G
• Description: IC SDRAM 64MBIT 133MHZ 54TSOP
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC8M8A2P-75:G

• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 64M (8M x 8)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 54-TSOP II
• Organization: 8Mx8
• Density: 64Mb
• Address Bus: 14b
• Access Time (max): 6/5.4ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 140mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 2:
Table 3:
General Description
PDF: 09005aef80725c0b/Source: 09005aef806fc13c
64MSDRAM_1.fm - Rev. N 12/08 EN
Speed Grade
-7E
-75
-7E
-75
-6
Key Timing Parameters
CL = CAS (READ) latency
64Mb SDRAM Part Numbers
Notes:
Clock Frequency
1. FBGA Device Decoder: http://www.micron.com/support/FBGA/FBGA.asp
The Micron
containing 67,108,864 bits. It is internally configured as a quad-bank DRAM with a
synchronous interface (all signals are registered on the positive edge of the clock signal,
CLK). Each of the x4’s 16,777,216-bit banks is organized as 4,096 rows by 1,024 columns
by 4 bits. Each of the x8’s 16,777,216-bit banks is organized as 4,096 rows by 512 columns
by 8 bits. Each of the x16’s 16,777,216-bit banks is organized as 4,096 rows by 256
columns by 16 bits.
Read and write accesses to the SDRAM are burst oriented; accesses start at a selected
location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select
the bank; A0–A11 select the row). The address bits registered coincident with the READ
or WRITE command are used to select the starting column location for the burst access.
The SDRAM provides for programmable read or write burst lengths of 1, 2, 4, or 8 loca-
tions, or the full page, with a burst terminate option. An auto precharge function may be
enabled to provide a self-timed row precharge that is initiated at the end of the burst
sequence.
The 64Mb SDRAM uses an internal pipelined architecture to achieve high-speed opera-
tion. This architecture is compatible with the 2n rule of prefetch architectures, but it also
allows the column address to be changed on every clock cycle to achieve a high-speed,
MT48LC16M4A2TG
MT48LC16M4A2P
MT48LC8M8A2TG
MT48LC8M8A2P
MT48LC4M16A2TG
MT48LC4M16A2P
MT48LC4M16A2B4
MT48LC4M16A2F4
166 MHz
143 MHz
133 MHz
133 MHz
100 MHz
Part Numbers
®
64Mb SDRAM is a high-speed CMOS, dynamic random-access memory
1
1
CL = 2
5.4ns
6ns
–
–
–
Access Time
2
Architecture
16 Meg x 4
16 Meg x 4
4 Meg x 16
4 Meg x 16
4 Meg x 16
4 Meg x 16
Micron Technology, Inc., reserves the right to change products or specifications without notice.
8 Meg x 8
8 Meg x 8
CL = 3
5.5ns
5.4ns
5.4ns
–
–
64Mb: x4, x8, x16 SDRAM
Setup Time
1.5ns
1.5ns
1.5ns
1.5ns
1.5ns
General Description
©2000 Micron Technology, Inc. All rights reserved.
54-ball VFBGA
54-ball VFBGA
54-pin TSOP II
54-pin TSOP II
54-pin TSOP II
54-pin TSOP II
54-pin TSOP II
54-pin TSOP II
Package
Hold Time
0.8ns
0.8ns
0.8ns
0.8ns
1ns