MT48LC8M8A2P-75:G Micron Technology Inc, MT48LC8M8A2P-75:G Datasheet - Page 40

• Manufacturer Part Number: MT48LC8M8A2P-75:G
• Description: IC SDRAM 64MBIT 133MHZ 54TSOP
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC8M8A2P-75:G

• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 64M (8M x 8)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 54-TSOP II
• Organization: 8Mx8
• Density: 64Mb
• Address Bus: 14b
• Access Time (max): 6/5.4ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 140mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 9:
PDF: 09005aef80725c0b/Source: 09005aef806fc13c
64MSDRAM_2.fm - Rev. N 12/08 EN
Current State
Row active
precharge
precharge
disabled)
disabled)
Write
(auto
(auto
Read
Any
Idle
Truth Table 3 – Current State Bank n, Command to Bank n
(Notes 1–6 apply to entire table; notes appear below and on next page)
Notes:
CS#
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
RAS#
1. This table applies when CKE
2. This table is bank-specific, except where noted; i.e., the current state is for a specific bank,
3. Current state definitions:
4. The following states must not be interrupted by a command issued to the same bank. COM-
5. The following states must not be interrupted by any executable command; COMMAND
X
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
after
and the commands shown are those allowed to be issued to that bank when in that state.
Exceptions are covered in the notes below.
MAND INHIBIT or NOP commands or allowable commands to the other bank should be
issued on any clock edge occurring during these states. Allowable commands to the other
bank are determined by its current state and Table 9 and according to Table 10 on page 42.
INHIBIT or NOP commands must be applied on each positive clock edge during these states.
precharge enabled:
precharge enabled:
Row active: A row in the bank has been activated, and
Refreshing: Starts with registration of an AUTO REFRESH command and ends when
t
CAS#
XSR has been met (if the previous state was self refresh).
Row activating: Starts with registration of an ACTIVE command and ends when
X
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
Write w/auto
Precharging: Starts with registration of a PRECHARGE command and ends when
Read w/auto
Write: A WRITE burst has been initiated, with auto precharge disabled, and has
Read: A READ burst has been initiated, with auto precharge disabled, and has
Idle: The bank has been precharged, and
WE#
H
H
H
H
H
H
bursts/accesses and no register accesses are in progress.
not yet terminated or been terminated.
not yet terminated or been terminated.
t
X
L
L
L
L
L
L
L
L
L
L
RC is met. After
t
is met. After
Starts with registration of a READ command with auto precharge
enabled and ends when
will be in the idle state.
Starts with registration of a WRITE command with auto precharge
enabled and ends when
will be in the idle state.
COMMAND INHIBIT (NOP/continue previous operation)
NO OPERATION (NOP/continue previous operation)
ACTIVE (Select and activate row)
AUTO REFRESH
LOAD MODE REGISTER
PRECHARGE
READ (Select column and start READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE (Deactivate row in bank or banks)
READ (Select column and start new READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE (Truncate READ burst, start precharge)
BURST TERMINATE
READ (Select column and start READ burst)
WRITE (Select column and start new WRITE burst)
PRECHARGE (Truncate WRITE burst, start precharge)
BURST TERMINATE
RP is met. After
n-1
40
was HIGH and CKE
t
RC is met, the SDRAM will be in the all banks idle state.
t
RCD is met, the bank will be in the row active state.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
RP is met, the bank will be in the idle state.
Command (Action)
t
t
RP has been met. After
RP has been met. After
n
is HIGH (see Table 8 on page 39) and
t
RP has been met.
64Mb: x4, x8, x16 SDRAM
t
RCD has been met. No data
©2000 Micron Technology, Inc. All rights reserved.
t
t
RP is met, the bank
RP is met, the bank
Commands
Notes
11
10
10
10
10
10
10
7
7
8
8
9
8
9
t
RCD