MT45W1MW16PDGA-70 IT TR Micron Technology Inc, MT45W1MW16PDGA-70 IT TR Datasheet
MT45W1MW16PDGA-70 IT TR
Specifications of MT45W1MW16PDGA-70 IT TR
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MT45W1MW16PDGA-70 IT TR Summary of contents
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... DQ1 DQ2 V Q DQ11 A17 A7 DQ3 DQ12 NC A16 DQ4 A15 DQ14 DQ13 A14 DQ5 DQ6 A13 DQ15 A19 A12 WE# DQ7 A18 A8 A9 A10 A11 NC Top View (Ball Down) Part Number Example: MT45W1MW16PDGA-70WT ©2005 Micron Technology, Inc. All rights reserved. Features CC SS ...
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... Maximum and Typical Standby Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Timing Diagrams .24 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Revision History .29 PDF: 09005aef81cadc83/Source:09005aef81c6edb4 16mb_asyncpage_cr1_0_p23zTOC.fm - Rev. F 4/08 EN 16Mb: 1 Meg x 16 Async/Page CellularRAM 1.0 Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. 2 Table of Contents ©2005 Micron Technology, Inc. All rights reserved. ...
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... WRITE Cycle (WE# Control .26 Figure 22: WRITE Cycle (CE# Control .26 Figure 23: WRITE Cycle (LB#/UB# Control .27 Figure 24: 48-Ball VFBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 PDF: 09005aef81cadc83/Source:09005aef81c6edb4 16mb_asyncpage_cr1_0_p23zLOF.fm - Rev. F 4/08 EN 16Mb: 1 Meg x 16 Async/Page CellularRAM 1.0 Memory ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 TCR ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 IH Micron Technology, Inc., reserves the right to change products or specifications without notice. 3 List of Figures ...
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... Table 12: Deep Power-Down Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Table 13: Initialization Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 PDF: 09005aef81cadc83/Source:09005aef81c6edb4 16mb_asyncpage_cr1_0_p23zLOT.fm - Rev. F 4/08 EN 16Mb: 1 Meg x 16 Async/Page CellularRAM 1.0 Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. 4 List of Tables ©2005 Micron Technology, Inc. All rights reserved. ...
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... To operate seamlessly on an asynchronous memory bus, CellularRAM products incor- porate a transparent self-refresh mechanism. The hidden refresh requires no additional support from the system memory controller and has no significant impact on device read/write performance. Special attention has been focused on current consumption during self refresh. Cellular- RAM products include three system-accessible mechanisms to minimize refresh cur- rent ...
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... Supply SS PDF: 09005aef81cadc83/Source:09005aef81c6edb4 16mb_asyncpage_cr1_0_p23z_2.fm - Rev. F 4/08 EN 16Mb: 1 Meg x 16 Async/Page CellularRAM 1.0 Memory Description Address inputs: Inputs for the address accessed during READ or WRITE operations. The address lines are also used to define the value to be loaded into the CR. Sleep enable: When ZZ# is LOW, the CR can be loaded or the device can enter one of two low-power modes (DPD or PAR) ...
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... When WE# is active, the OE# input is internally disabled and has no effect on the I/Os. 4. The device will consume active power in this mode whenever addresses are changed standby current. 6. DPD is enabled when configuration register bit CR[4] is “0”; otherwise, PAR is enabled. PDF: 09005aef81cadc83/Source:09005aef81c6edb4 16mb_asyncpage_cr1_0_p23z_2.fm - Rev. F 4/08 EN 16Mb: 1 Meg x 16 Async/Page CellularRAM 1.0 Memory CE# WE# OE# LB#/UB ...
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... To view the location of the abbreviated mark on the device, refer to customer service note, CSN-11, “Product Mark/Label,” at http://www.micron.com/csn. PDF: 09005aef81cadc83/Source:09005aef81c6edb4 16mb_asyncpage_cr1_0_p23z_2.fm - Rev. F 4/08 EN 16Mb: 1 Meg x 16 Async/Page CellularRAM 1.0 Memory WT ES http://www.micron.com/partsearch Micron Technology, Inc., reserves the right to change products or specifications without notice. 8 ...
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... OE#. The data to be written will be latched on the rising edge of CE#, WE#, or LB#/UB# (whichever occurs first). WE# LOW time must be limited to PDF: 09005aef81cadc83/Source:09005aef81c6edb4 16mb_asyncpage_cr1_0_p23z_2.fm - Rev. F 4/08 EN 16Mb: 1 Meg x 16 Async/Page CellularRAM 1.0 Memory Q must be applied simultaneously, and when they reach a stable level above Micron Technology, Inc ...
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... DATA LB#/UB# Figure 6: WRITE Operation CE# OE# WE# ADDRESS DATA LB#/UB# PDF: 09005aef81cadc83/Source:09005aef81c6edb4 16mb_asyncpage_cr1_0_p23z_2.fm - Rev. F 4/08 EN 16Mb: 1 Meg x 16 Async/Page CellularRAM 1.0 Memory ADDRESS VALID DATA VALID READ Cycle Time DON’T CARE t < CEM ADDRESS VALID DATA VALID WRITE Cycle Time DON’T CARE Micron Technology, Inc ...
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... During READ operations, enabled bytes are driven onto the DQ. The DQ associated with a disabled byte are put into a High-Z state during a READ operation. During WRITE operations, any disabled bytes will not be transferred to the memory array and the internal value will remain unchanged. During a WRITE cycle, the data to be written is latched on the rising edge of CE#, WE#, LB#, or UB#, whichever occurs first ...
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... Partial-array refresh (PAR) restricts refresh operation to a portion of the total memory array. This feature enables the system to reduce refresh current by only refreshing that part of the memory array that is absolutely necessary. The refresh options are full array, one-half array, one-quarter array, one-eighth array, or none of the array. Data stored in addresses not receiving refresh will become corrupted ...
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... Driving ZZ# LOW will place the device in the PAR mode if the SLEEP bit in the CR has been set HIGH (CR[4] = 1). The device should not be put into DPD using CR software access. PDF: 09005aef81cadc83/Source:09005aef81c6edb4 16mb_asyncpage_cr1_0_p23z_2.fm - Rev. F 4/08 EN 16Mb: 1 Meg x 16 Async/Page CellularRAM 1.0 Memory Power-Up To enable PAR, bring ZZ# LOW for 10µs. ...
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... CR. The use of the software sequence does not affect the ability to perform the standard (ZZ#-controlled) method of loading the CR. PDF: 09005aef81cadc83/Source:09005aef81c6edb4 16mb_asyncpage_cr1_0_p23z_2.fm - Rev. F 4/08 EN 16Mb: 1 Meg x 16 Async/Page CellularRAM 1.0 Memory ADDRESS VALID t < 500ns Q if the system will use DPD; DPD cannot be enabled or disabled using the CC Micron Technology, Inc ...
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... DATA Note: If the data at the falling edge of WE# is not 0000h possible that the data stored at the highest memory location will be altered. PDF: 09005aef81cadc83/Source:09005aef81c6edb4 16mb_asyncpage_cr1_0_p23z_2.fm - Rev. F 4/08 EN 16Mb: 1 Meg x 16 Async/Page CellularRAM 1.0 Memory Configuration Register Operation READ READ WRITE ADDRESS ADDRESS ...
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... Partial-Array Refresh (CR[2:0]) Default = Full-Array Refresh The PAR bits restrict refresh operation to a portion of the total memory array. This fea- ture allows the system to reduce current by only refreshing that part of the memory array required by the host system. The refresh options are full array, one-half array, one-quar- ter array, one-eighth array, or none of the array ...
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... PDF: 09005aef81cadc83/Source:09005aef81c6edb4 16mb_asyncpage_cr1_0_p23z_2.fm - Rev. F 4/08 EN 16Mb: 1 Meg x 16 Async/Page CellularRAM 1.0 Memory Active Section Address Space Full die 00000h–FFFFFh One-half of die 00000h–7FFFFh One-quarter of die 00000h–3FFFFh One-eighth of die 00000h–1FFFFh None of die 0 One-half of die 80000h–FFFFFh One-quarter of die C0000h–FFFFFh One-eighth of die E0000h– ...
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... Operating temperature (case) 1 Wireless Industrial Soldering temperature and time 10 seconds (solder ball only) Notes: 1. –30°C exceeds the CellularRAM Workgroup 1.0 specification of –25°C. PDF: 09005aef81cadc83/Source:09005aef81c6edb4 16mb_asyncpage_cr1_0_p23z_2.fm - Rev. F 4/08 EN 16Mb: 1 Meg x 16 Async/Page CellularRAM 1.0 Memory –0.5V to (4. relative Electrical Characteristics Rating ...
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... SB achieve low standby current, all inputs must be driven to V higher for up to 500ms after power-up or when entering standby mode. PDF: 09005aef81cadc83/Source:09005aef81c6edb4 16mb_asyncpage_cr1_0_p23z_2.fm - Rev. F 4/08 EN 16Mb: 1 Meg x 16 Async/Page CellularRAM 1.0 Memory 1 (–30ºC ≤ T ≤ +85 ºC), Industrial temperature (–40ºC < Conditions ...
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... Note: Typical I sensor enabled. PDF: 09005aef81cadc83/Source:09005aef81c6edb4 16mb_asyncpage_cr1_0_p23z_2.fm - Rev. F 4/08 EN 16Mb: 1 Meg x 16 Async/Page CellularRAM 1.0 Memory +15°C (CR[6:5] = 10b) +45°C (CR[6:5] = 01b TCR Temperature (°C) currents for each PAR setting with the appropriate TCR selected, or temperature SB Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... Input timing begins at V the input test point may not be shown to scale. 3. Output timing ends at V Figure 15: Output Load Circuit DUT PDF: 09005aef81cadc83/Source:09005aef81c6edb4 16mb_asyncpage_cr1_0_p23z_2.fm - Rev. F 4/08 EN 16Mb: 1 Meg x 16 Async/Page CellularRAM 1.0 Memory Conditions 0V; +25° ZZ CR[ ...
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... V 2. Low-Z to High-Z timings are tested with the circuit shown in Figure 15 on page 21. The High-Z timings measure a 100mV transition from either V 3. Page mode enabled only. PDF: 09005aef81cadc83/Source:09005aef81c6edb4 16mb_asyncpage_cr1_0_p23z_2.fm - Rev. F 4/08 EN 16Mb: 1 Meg x 16 Async/Page CellularRAM 1.0 Memory Symbol APA ...
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... Write cycle time Write pulse width Write recovery time ZZ# LOW to WE# LOW Table 12: Deep Power-Down Timing Requirements Description Chip deselect to ZZ# LOW Deep power-down recovery Minimum ZZ# pulse width PDF: 09005aef81cadc83/Source:09005aef81c6edb4 16mb_asyncpage_cr1_0_p23z_2.fm - Rev. F 4/08 EN 16Mb: 1 Meg x 16 Async/Page CellularRAM 1.0 Memory Symbol CPH t CW ...
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... Table 13: Initialization Timing Parameters Parameter Initialization period (required before normal operations) Figure 17: Load Configuration Register ADDRESS CE# LB#/UB# WE# OE# ZZ# Figure 18: Deep Power-Down – Entry/Exit ZZ# CE# PDF: 09005aef81cadc83/Source:09005aef81c6edb4 16mb_asyncpage_cr1_0_p23z_2.fm - Rev. F 4/08 EN 16Mb: 1 Meg x 16 Async/Page CellularRAM 1.0 Memory OPCODE CDZZ ZZWE t CDZZ ...
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... Figure 19: Single READ Operation (WE ADDRESS LB#/UB# DATA-OUT Figure 20: Page Mode READ Operation (WE ADDRESS A[19:4] ADDRESS A[3:0] LB#/UB# DATA-OUT PDF: 09005aef81cadc83/Source:09005aef81c6edb4 16mb_asyncpage_cr1_0_p23z_2.fm - Rev. F 4/08 EN 16Mb: 1 Meg x 16 Async/Page CellularRAM 1.0 Memory ) ADDRESS VALID BLZ t OE OE# t OLZ High-Z DON’T CARE ...
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... Figure 21: WRITE Cycle (WE# Control) ADDRESS LB#/UB# WE# DATA-IN DATA-OUT Figure 22: WRITE Cycle (CE# Control) ADDRESS LB#/UB# WE# DATA-IN DATA-OUT PDF: 09005aef81cadc83/Source:09005aef81c6edb4 16mb_asyncpage_cr1_0_p23z_2.fm - Rev. F 4/08 EN 16Mb: 1 Meg x 16 Async/Page CellularRAM 1.0 Memory t WC ADDRESS VALID CE OE# t WHZ t WC ADDRESS VALID CE OE WHZ 26 Timing Diagrams t WR ...
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... Figure 23: WRITE Cycle (LB#/UB# Control) ADDRESS LB#/UB# WE# DATA-IN DATA-OUT PDF: 09005aef81cadc83/Source:09005aef81c6edb4 16mb_asyncpage_cr1_0_p23z_2.fm - Rev. F 4/08 EN 16Mb: 1 Meg x 16 Async/Page CellularRAM 1.0 Memory t WC ADDRESS VALID CE OE WHZ 27 Timing Diagrams DATA VALID High-Z DON’T CARE Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range for production devices. Although considered final, these specifications are subject to change, as further product development and data characterization PDF: 09005aef81cadc83/Source:09005aef81c6edb4 16mb_asyncpage_cr1_0_p23z_2.fm - Rev. F 4/08 EN 16Mb: 1 Meg x 16 Async/Page CellularRAM 1.0 Memory 3.75 0.75 TYP ...
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... Updated “TBD” standby values Rev 08/05 • Initial release; Advance PDF: 09005aef81cadc83/Source:09005aef81c6edb4 16mb_asyncpage_cr1_0_p23z_2.fm - Rev. F 4/08 EN 16Mb: 1 Meg x 16 Async/Page CellularRAM 1.0 Memory t PU from a MIN to MAX value in Table 13 on page 24. Micron Technology, Inc., reserves the right to change products or specifications without notice. 29 Revision History © ...