MT48LC32M8A2P-7E:D Micron Technology Inc, MT48LC32M8A2P-7E:D Datasheet
MT48LC32M8A2P-7E:D
Specifications of MT48LC32M8A2P-7E:D
Related parts for MT48LC32M8A2P-7E:D
MT48LC32M8A2P-7E:D Summary of contents
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SDR SDRAM MT48LC64M4A2 – 16 Meg banks MT48LC32M8A2 – 8 Meg banks MT48LC16M16A2 – 4 Meg banks Features • PC100- and PC133-compliant • Fully synchronous; all signals registered ...
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... Table 3: 256Mb SDR Part Numbering Part Numbers MT48LC64M4A2TG MT48LC64M4A2P 1 MT48LC64M4A2FB 1 MT48LC64M4A2BB MT48LC32M8A2TG MT48LC32M8A2P 1 MT48LC32M8A2FB 1 MT48LC32M8A2BB MT48LC16M16A2TG MT48LC16M16A2P MT48LC16M16A2FG MT48LC16M16A2BG 1. Actual FBGA part marking is shown in Package Dimensions (page 16). Note: FBGA Part Marking Decoder Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the part number. Micron’ ...
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Contents General Description ......................................................................................................................................... 8 Automotive Temperature ............................................................................................................................. 8 Functional Block Diagrams ............................................................................................................................... 9 Pin and Ball Assignments and Descriptions ..................................................................................................... 12 Package Dimensions ...................................................................................................................................... 16 Temperature and Thermal Impedance ............................................................................................................ 19 Electrical Specifications .................................................................................................................................. 22 Electrical Specifications – I ...
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Rev. E – 3/02 ............................................................................................................................................... 91 Rev. D – 7/01 .............................................................................................................................................. 91 Rev. C – 3/01 .............................................................................................................................................. 91 Rev. B – 10/00 ............................................................................................................................................. 92 Rev. A – 11/99 ............................................................................................................................................. 92 PDF: 09005aef8091e6d1 256Mb_sdr.pdf - Rev. N 1/10 EN 256Mb: x4, ...
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List of Tables Table 1: Address Table .................................................................................................................................... 1 Table 2: Key Timing Parameters ...................................................................................................................... 1 Table 3: 256Mb SDR Part Numbering ............................................................................................................... 2 Table 4: Pin and Ball Descriptions .................................................................................................................. 15 Table 5: Temperature Limits .......................................................................................................................... 19 Table 6: ...
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List of Figures Figure 1: 64 Meg x 4 Functional Block Diagram ................................................................................................ 9 Figure 2: 32 Meg x 8 Functional Block Diagram .............................................................................................. 10 Figure 3: 16 Meg x 16 Functional Block Diagram ............................................................................................. 11 Figure 4: 54-Pin TSOP ...
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Figure 51: Auto Refresh Mode ........................................................................................................................ 82 Figure 52: Self Refresh Mode ......................................................................................................................... 84 Figure 53: Power-Down Mode ....................................................................................................................... 85 Figure 54: Clock Suspend During WRITE Burst ............................................................................................... 86 Figure 55: Clock Suspend During READ Burst ................................................................................................ 87 Figure 56: ...
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... Precharging one bank while accessing one of the other three banks will hide the PRECHARGE cycles and provide seamless, high-speed, random- access operation. The 256Mb SDRAM is designed to operate in 3.3V memory systems. An auto refresh mode is provided, along with a power-saving, power-down mode. All inputs and out- puts are LVTTL-compatible. ...
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... READ DATA LATCH CONTROL WRITE DRIVERS LOGIC 2 COLUMN- 11 ADDRESS COUNTER/ LATCH 9 256Mb: x4, x8, x16 SDRAM Functional Block Diagrams BANK3 BANK2 BANK1 BANK0 MEMORY 1 ARRAY DATA OUTPUT 4 REGISTER 8192 I/O GATING DATA INPUT 4 2048 REGISTER (x4) COLUMN DECODER Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
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... READ DATA LATCH CONTROL WRITE DRIVERS LOGIC 2 COLUMN- 10 ADDRESS COUNTER/ LATCH 10 256Mb: x4, x8, x16 SDRAM Functional Block Diagrams BANK3 BANK2 BANK1 BANK0 MEMORY 1 ARRAY DATA OUTPUT 8 REGISTER 8192 I/O GATING DATA INPUT 8 1024 REGISTER (x8) COLUMN DECODER Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
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... BA[1:0] REGISTER 2 9 PDF: 09005aef8091e6d1 256Mb_sdr.pdf - Rev. N 1/10 EN BANK1 13 BANK0 ROW- 13 ADDRESS ROW- BANK0 ADDRESS MUX MEMORY 8192 LATCH ARRAY & (8192 x 512 x 16) DECODER SENSE AMPLIFIERS 8192 I/O GATING 2 DQM MASK LOGIC BANK READ DATA LATCH CONTROL WRITE DRIVERS LOGIC ...
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Pin and Ball Assignments and Descriptions Figure 4: 54-Pin TSOP (Top View DQ0 - NC DQ0 DQ1 - NC NC DQ2 - NC DQ1 DQ3 - ...
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Figure 5: 60-Ball FBGA (Top View) 64 Meg x 4 SDRAM 8mm x 16mm SSQ C V DQ3 DDQ SSQ F V ...
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Figure 6: 54-Ball VFBGA (Top View DQ14 C DQ12 D DQ10 E F UDQM The balls at A4, A5, and A6 are absent from the physical package. They are included to Note: PDF: 09005aef8091e6d1 ...
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... Address inputs: A[12:0] are sampled during the ACTIVE command (row address A[12:0]) and READ or WRITE command (column address A[9:0] and A11 for x4; A[9:0] for x8; A[8:0] for x16; with A10 defining auto precharge) to select one location out of the memory array in the re- spective bank. A10 is sampled during a PRECHARGE command to determine if all banks are to be precharged (A10 HIGH) or bank selected by BA[1:0] (LOW) ...
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Package Dimensions Figure 7: 54-Pin Plastic TSOP (400 mil) PIN # 0. 1.00 10.16 ±0.08 11.76 ±0.20 +0.03 0.15 -0.02 1. All dimensions are in millimeters. Notes: 2. Package width and length do not include ...
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Figure 8: 60-Ball FBGA "FB" (8mm x 16mm) (x4, x8) 0.155 ±0.013 0.850 ±0.05 60X Ø 0.45 DIMENSIONS APPLY TO SOLDER BALLS POST REFLOW. PRE- REFLOW DIAMETER IS 0. 0.33 NSMD BALL PAD. BALL A8 8.00 ±0.05 16.00 ...
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Figure 9: 54-Ball VFBGA "FG" (8mm x 14mm) (x16) 0.65 ±0.05 SEATING PLANE C 0.10 C 54X Ø0.45 SOLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION. THE PRE- REFLOW DIAMETER IS Ø0.42 BALL A9 6.40 3.20 ±0.05 3.20 ±0.05 1. ...
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Temperature and Thermal Impedance It is imperative that the SDRAM device’s temperature specifications, shown in Table 5 (page 19), be maintained to ensure the junction temperature is in the proper operat- ing range to meet data sheet specifications. An important ...
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Table 6: Thermal Impedance Simulated Values Die Revision Package Substrate D 54-pin TSOP 2-layer 4-layer 54-ball VFBGA 2-layer 4-layer 60-ball FBGA 2-layer 4-layer 1. For designs expected to last beyond the die revision listed, contact Micron Applications Notes: 2. Thermal ...
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Figure 11: Example: Temperature Test Point Location, 54-Ball VFBGA (Top View) Figure 12: Example: Temperature Test Point Location, 60-Ball FBGA (Top View) PDF: 09005aef8091e6d1 256Mb_sdr.pdf - Rev. N 1/10 EN Temperature and Thermal Impedance 8.00mm 4.00mm Test point 8.00mm 4.00mm ...
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Electrical Specifications Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other condi- tions above those indicated in the operational sections ...
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Table 9: Capacitance Note 1 applies to all parameters and conditions Package Parameter TSOP "TG" package Input capacitance: CLK Input capacitance: All other input-only balls Input/output capacitance: DQ FBGA "FB" and "FG" packages Input capacitance: CLK Input capacitance: All other ...
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Electrical Specifications – I Table 10: I Specifications and Conditions (-6A) DD Notes 1–5 apply to all parameters and conditions; V Parameter/Condition Operating current: Active mode; Burst = 2; READ or WRITE; Standby current: Power-down mode; All banks idle; CKE ...
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Enables on-chip refresh and address counters. 8. Other input signals are allowed to transition no more than once every two clocks and 9. The I 10. Address transitions average one transition every two clocks. 11. ...
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Electrical Specifications – AC Operating Conditions Table 12: Electrical Characteristics and Recommended AC Operating Conditions (-6A) Notes and 20 apply to all parameters and conditions Parameter Access time from CLK (positive edge) Address hold time ...
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Table 13: Electrical Characteristics and Recommended AC Operating Conditions (-7E, -75) Notes and 20 apply to all parameters and conditions Parameter Access time from CLK (positive edge) Address hold time Address setup time CLK high-level ...
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Table 14: AC Functional Characteristics (-6A) Notes 1–5 and note 7 apply to all parameters and conditions Parameter Last data-in to burst STOP command READ/WRITE command to READ/WRITE command Last data-in to new READ/WRITE command CKE to clock disable or ...
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Table 15: AC Functional Characteristics (-7E, -75) Notes 1–5 and note 7 apply to all parameters and conditions Parameter Last data-in to burst STOP command READ/WRITE command to READ/WRITE command Last data-in to new READ/WRITE command CKE to clock disable ...
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Required clocks are specified by JEDEC functionality and are not dependent on any tim- 12. CLK must be toggled a minimum of two times during this period. 13. Based on 14. The clock frequency must remain constant (stable clock ...
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Functional Description In general, 256Mb SDRAM devices (16 Meg banks, 8 Meg banks, and 4 Meg banks) are quad-bank DRAM that operate at 3.3V and include a synchronous ...
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Commands The following table provides a quick reference of available commands, followed by a written description of each command. Additional Truth Tables (Table 17 (page 38), Table 18 (page 40), and Table 19 (page 42)) provide current state/next state informa- ...
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NO OPERATION (NOP) The NO OPERATION (NOP) command is used to perform a NOP to the selected device (CS# is LOW). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. ...
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READ The READ command is used to initiate a burst read access to an active row. The values on the BA0 and BA1 inputs select the bank; the address provided selects the starting column location. The value on input A10 ...
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... Input data appearing on the DQ is written to the memory array, subject to the DQM input logic level appearing coincident with the data given DQM signal is registered LOW, the corresponding data is written to memory ...
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PRECHARGE The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access a specified time ( whether one or all ...
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AUTO REFRESH AUTO REFRESH is used during normal operation of the SDRAM and is analogous to CAS#- BEFORE-RAS# (CBR) refresh in conventional DRAMs. This command is nonpersistent must be issued each time a refresh is required. All active ...
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Truth Tables Table 17: Truth Table – Current State Bank n, Command to Bank n Notes 1–6 apply to all parameters and conditions Current State CS# Any H L Idle Row active Read ...
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The following states must not be interrupted by any executable command; COMMAND 6. All states and sequences not shown are illegal or reserved. 7. Not bank specific; requires that all banks are idle. 8. Does not affect the state ...
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Table 18: Truth Table – Current State Bank n, Command to Bank m Notes 1–6 apply to all parameters and conditions Current State CS# Any H L Idle X Row activating, active precharging Read L ...
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AUTO REFRESH, SELF REFRESH, and LOAD MODE REGISTER commands can only be is BURST TERMINATE command cannot be issued to another bank; it applies to the bank 6. All states and sequences not shown are illegal or ...
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Table 19: Truth Table – CKE Notes 1–4 apply to all parameters and conditions Current State CKE n-1 Power-down L Self refresh Clock suspend Power-down L Self refresh Clock suspend All banks idle H All banks idle Reading or writing ...
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Initialization SDRAM must be powered up and initialized in a predefined manner. Operational proce- dures other than those specified may result in undefined operation. After power is applied signal cycling within timing constraints specified for the ...
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At this point the DRAM is ready for any valid command. Note: More than two AUTO REFRESH commands can be issued in the sequence. After steps 9 and 10 are complete, repeat them until the desired number of AUTO REFRESH ...
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Figure 17: Initialize and Load Mode Register CKH t CKS ( ( ) ) CKE ( ( ) ) t CMS t CMH ( ( ) ) COMMAND NOP PRECHARGE ...
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Mode Register The mode register defines the specific mode of operation, including burst length (BL), burst type, CAS latency (CL), operating mode, and write burst mode. The mode register is programmed via the LOAD MODE REGISTER command and retains the ...
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Figure 18: Mode Register Definition A11 A12 12 11 Reserved Program BA1, BA0 = “0, 0” to ensure compatibility with future devices. Write Burst Mode M9 0 Programmed Burst Length 1 Single Location Access M8 M7 M6- Defined ...
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Burst Length Read and write accesses to the device are burst oriented, and the burst length (BL) is programmable. The burst length determines the maximum number of column loca- tions that can be accessed for a given READ or WRITE ...
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Table 20: Burst Definition Table Burst Length Starting Column Address Continuous n = A0–An/9/8 ...
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CAS Latency The CAS latency (CL) is the delay, in clock cycles, between the registration of a READ command and the availability of the output data. The latency can be set to two or three clocks READ command ...
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Bank/Row Activation Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row in that bank must be opened. This is accomplished via the ACTIVE command, which selects both the bank and the row ...
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READ Operation READ bursts are initiated with a READ command, as shown in Figure 14 (page 34). The starting column and bank addresses are provided with the READ command, and auto precharge is either enabled or disabled for that burst ...
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Figure 21: Consecutive READ Bursts Command Address Command Address 1. Each READ command can be issued to any bank. DQM is LOW. Note: PDF: 09005aef8091e6d1 256Mb_sdr.pdf - Rev CLK READ NOP NOP Bank, Col ...
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Figure 22: Random READ Accesses Command Address Command Address 1. Each READ command can be issued to any bank. DQM is LOW. Note: Data from any READ burst can be truncated with a subsequent WRITE command, and data from a ...
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The DQM signal must be de-asserted prior to the WRITE command (DQM latency is zero clocks for input buffers) to ensure that the written data is not masked. Figure 23 (page 55) shows where, due to the clock cycle frequency, ...
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Figure 24: READ-to-WRITE With Extra Clock Cycle DQM Command Address The READ command can be issued to any bank, and the WRITE command can be Note: Figure 25: READ-to-PRECHARGE Command Address Command Address 1. DQM is ...
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Continuous-page READ bursts can be truncated with a BURST TERMINATE command and fixed-length READ bursts can be truncated with a BURST TERMINATE command, provided that auto precharge was not activated. The BURST TERMINATE command should be issued x cycles before ...
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Figure 27: Alternating Bank Read Accesses CLK t CKS t CKH CKE t CMS t CMH Command ACTIVE NOP t CMS DQM Row Address Enable auto precharge Row ...
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Figure 28: READ Continuous Page Burst CLK CKS t CKH CKE t CMS t CMH Command ACTIVE NOP t CMS DQM Address Row Column ...
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Figure 29: READ – DQM Operation CLK t CKS t CKH CKE t CMS t CMH Command ACTIVE NOP t CMS DQM Row Address Enable auto precharge A10 ...
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WRITE Operation WRITE bursts are initiated with a WRITE command, as shown in Figure 15 (page 35). The starting column and bank addresses are provided with the WRITE command and auto precharge is either enabled or disabled for that access. ...
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Figure 31: WRITE-to-WRITE Command Address 1. DQM is LOW. Each WRITE command may be issued to any bank. Note: Data for any WRITE burst can be truncated with a subsequent READ command, and data for a fixed-length WRITE burst can ...
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Figure 32: Random WRITE Cycles Command Address Note: 1. Each WRITE command can be issued to any bank. DQM is LOW. Figure 33: WRITE-to-READ Command Address 1. The WRITE command can be issued to any bank, and the READ command ...
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Figure 34: WRITE-to-PRECHARGE Command Address Command Address 1. In this example DQM could remain LOW if the WRITE burst is a fixed length of two. Note: Fixed-length WRITE bursts can be truncated with the ...
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Figure 35: Terminating a WRITE Burst Command Address 1. DQM is LOW. Note: PDF: 09005aef8091e6d1 256Mb_sdr.pdf - Rev CLK BURST NEXT WRITE TERMINATE COMMAND Bank, Address Col Data IN Transitioning data ...
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Figure 36: Alternating Bank Write Accesses CLK t CKS t CKH CKE t CMS t CMH Command ACTIVE NOP t CMS DQM Row Address Column ...
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Figure 37: WRITE – Continuous Page Burst CLK CKS t CKH CKE t CMS t CMH Command ACTIVE NOP DQM Address Row Row A10 t ...
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Figure 38: WRITE – DQM Operation CLK t CKS t CKH CKE t CMS t CMH Command ACTIVE NOP DQM Address Row Row A10 ...
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PRECHARGE Operation The PRECHARGE command (see Figure 16 (page 36)) is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a sub- sequent row access some ...
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The last valid data WRITE to bank n will be data registered one clock prior to a WRITE to bank m (see Figure 46 (page 76)). Figure 39: READ With Auto Precharge Interrupted by a READ CLK Command Bank ...
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Figure 40: READ With Auto Precharge Interrupted by a WRITE CLK Command Page Bank n active Internal States Bank m Address 1 DQM DQ Note: 1. DQM is HIGH prevent D PDF: 09005aef8091e6d1 256Mb_sdr.pdf - Rev. N ...
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Figure 41: READ With Auto Precharge CLK t CKS t CKH CKE t CMS t CMH Command ACTIVE NOP t CMS DQM Row Address Enable auto precharge Row ...
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Figure 42: READ Without Auto Precharge CLK t CKS t CKH CKE t CMS t CMH Command ACTIVE NOP DQM Address Row A10 Row Disable auto precharge t ...
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Figure 43: Single READ With Auto Precharge CLK t CKS t CKH CKE t CMS t CMH Command ACTIVE NOP DQM Address Row A10 Row ...
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Figure 44: Single READ Without Auto Precharge CLK t CKS t CKH CKE t CMS t CMH Command ACTIVE NOP DQM Address Row A10 Row ...
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Figure 45: WRITE With Auto Precharge Interrupted by a READ CLK Command Bank n Internal States Bank m Address DQ 1. DQM is LOW. Note: Figure 46: WRITE With Auto Precharge Interrupted by a WRITE CLK Command Bank n Internal ...
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Figure 47: WRITE With Auto Precharge CLK t CKS t CKH CKE t CMS t CMH Command ACTIVE NOP t CMS DQM Address Row Column ...
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Figure 48: WRITE Without Auto Precharge CLK t CKS t CKH CKE t CMS t CMH Command ACTIVE NOP t CMS DQM Address Row Column ...
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Figure 49: Single WRITE With Auto Precharge CLK t CKS t CKH CKE t CMS t CMH Command ACTIVE NOP DQM Address Row Enable auto precharge A10 Row ...
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Figure 50: Single WRITE Without Auto Precharge CLK t CKS t CKH CKE t CMS t CMH Command ACTIVE NOP DQM Row Address A10 Row Disable auto precharge ...
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AUTO REFRESH Operation The AUTO REFRESH command is used during normal operation of the device to refresh the contents of the array. This command is nonpersistent must be issued each time a refresh is required. All active banks ...
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Figure 51: Auto Refresh Mode T0 T1 CLK t CK CKE t CKS t CKH t CMS t CMH Command PRECHARGE DQM Address All banks A10 Single bank BA0, BA1 Bank(s) High Precharge ...
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SELF REFRESH Operation The self refresh mode can be used to retain data in the device, even when the rest of the system is powered down. When in self refresh mode, the device retains data without external clocking. The SELF ...
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Figure 52: Self Refresh Mode T0 T1 CLK t CK CKE t CKS t CKH t CMS t CMH Command PRECHARGE NOP DQM Address All banks A10 Single bank BA0, BA1 Bank(s) High ...
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Power-Down Power-down occurs if CKE is registered LOW coincident with a NOP or COMMAND IN- HIBIT when no accesses are in progress. If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down ...
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Clock Suspend The clock suspend mode occurs when a column access/burst is in progress and CKE is registered LOW. In the clock suspend mode, the internal clock is deactivated, freezing the synchronous logic. For each positive clock edge on which ...
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Figure 55: Clock Suspend During READ Burst CLK CKE Internal clock Command Address DQ 1. For this example greater, and DQM is LOW. Note: PDF: 09005aef8091e6d1 256Mb_sdr.pdf - Rev ...
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Figure 56: Clock Suspend Mode CLK t CKS CKE t CKS t CKH t CMS t CMH Command READ NOP t CMS t CMH DQM Address Column ...
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Revision History Rev. N – 1/10 • Updated format. • Used LPSDR as base and replaced with SDR-specific information as needed. Rev. M – 11/08 • Added Automotive Temperature documentation to datasheet: – Front-page Options table. – General Description section, ...
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Reworded table sub-title notes for DC Electrical Characteristics and Operating Char- acteristics, I (-7E, -75), Capacitance, Electrical Characteristics and Recommended AC Operating Conditions (-6A), and Electrical Characteristics and Recommended AC Operating Con- ditions (-7E, -75) tables. • Moved AC ...
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Rev. E – 3/02 • Added 54-ball FBGA package information to front page. • Added 54-ball FBGA pinout drawing to then-page 3. • Added 54-ball FBGA package part numbers to then-page 4. • Added 54-ball FBGA pin descriptions to then-page ...
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Updated diagram to correct page 50. • Updated single write with AP note note 3, and page 52. • Updated alternating bank write access, aligned page 53. • Added new page with "FB" FBGA ...