MT48V8M16LFB4-8:G Micron Technology Inc, MT48V8M16LFB4-8:G Datasheet

IC SDRAM 128MBIT 125MHZ 54VFBGA

MT48V8M16LFB4-8:G

Manufacturer Part Number
MT48V8M16LFB4-8:G
Description
IC SDRAM 128MBIT 125MHZ 54VFBGA
Manufacturer
Micron Technology Inc
Type
Mobile SDRAMr

Specifications of MT48V8M16LFB4-8:G

Format - Memory
RAM
Memory Type
Mobile SDRAM
Memory Size
128M (8Mx16)
Speed
125MHz
Interface
Parallel
Voltage - Supply
2.3 V ~ 2.7 V
Operating Temperature
0°C ~ 70°C
Package / Case
54-VFBGA
Organization
8Mx16
Density
128Mb
Address Bus
14b
Access Time (max)
19/8/7ns
Maximum Clock Rate
125MHz
Operating Supply Voltage (typ)
2.5V
Package Type
VFBGA
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.3V
Supply Current
100mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Mobile SDRAM
MT48LC8M16LF, MT48V8M16LF, MT48LC4M32LF, MT48V4M32LF
Features
• Temperature-compensated self refresh (TCSR)
• Fully synchronous; all signals registered on positive
• Internal pipelined operation; column address can be
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto precharge, includes concurrent auto precharge,
• Self refresh mode; standard and low power (not
• Auto refresh
• LVTTL-compatible inputs and outputs
• Low voltage power supply
• Partial-array self refresh (PASR) power-saving mode
Table 1:
PDF: 09005aef807f4885/Source: 09005aef8071a76b
128Mbx16x32Mobile_1.fm - Rev. M 1/09 EN
Speed
Grade
-75M
-75M
edge of system clock
changed every clock cycle
and auto refresh modes
available on AT devices)
– 64ms, 4,096-cycle refresh (15.6µs/row)
– 16ms, 4,096-cycle refresh (3.9µs/row)
-10
-10
-10
-8
-8
-8
(commercial and industrial)
(automotive)
Frequency
133 MHz
125 MHz
100 MHz
100 MHz
100 MHz
83 MHz
50 MHz
40 MHz
Clock
Key Timing Parameters
CL = CAS (READ) latency
Products and specifications discussed herein are subject to change by Micron without notice.
CL = 1 CL = 2 CL = 3
19ns
22ns
Access Time
8ns
8ns
6
7ns
7ns
5.4
t
19ns 19ns
20ns 20ns
20ns 20ns
19ns 19ns
20ns 20ns
20ns 20ns
20ns 20ns
20ns 20ns
RCD
t
RP
1
Options
• V
• Configurations
• Package/ball out
• Timing (cycle time)
• Temperature
• Design revision
Notes: 1. x16 only.
Table 2:
Configuration
Refresh count
Row addressing
Bank addressing
Column
addressing
– 3.3V/3.3V
– 2.5V/2.5–1.8V
– 8 Meg x 16 (2 Meg x 16 x 4 banks)
– 4 Meg x 32 (1 Meg x 32 x 4 banks)
– 54-ball VFBGA (8mm x 8mm)
– 54-ball VFBGA (8mm x 8mm)
– 90-ball VFBGA (8mm x 13mm)
– 90-ball VFBGA (8mm x 13mm)
– 54-pin TSOP II (400 mil)
– 54-pin TSOP II (400 mil) Pb-free
– 7.5ns @ CL = 3 (133 MHz)
– 8ns @ CL = 3 (125 MHz)
– 10ns @ CL = 3 (100 MHz)
– Commercial (0°C to +70°C)
– Industrial (–40°C to +85°C)
– Automotive (–40°C to +105°C)
DD
Micron Technology, Inc., reserves the right to change products or specifications without notice.
/V
2. x32 only.
3. Contact Micron for availability.
DD
Q
128Mb: x16, x32 Mobile SDRAM
Configurations
MT48V8M16LFB4-8:G
Part Number Example:
2 Meg x 16 x 4
4 (BA0, BA1)
4K (A0–A11)
8 Meg x 16
512 (A0–A8)
banks
4K
©2001 Micron Technology, Inc. All rights reserved.
1
1
2
2
Pb-free
Pb-free
1 Meg x 32 x 4
4 (BA0, BA1)
4K (A0–A11)
4 Meg x 32
256 (A0–A7)
banks
Features
4K
Mark
-75M
8M16
4M32
None
-10
TG
AT
LC
B4
B5
F4
F5
P
:G
-8
IT
V
3
3
3
3
3

Related parts for MT48V8M16LFB4-8:G

MT48V8M16LFB4-8:G Summary of contents

Page 1

... Pb-free 2 2 Pb-free Configurations 8 Meg Meg Meg Meg banks banks 4K 4K (A0–A11) 4K (A0–A11) 4 (BA0, BA1) 4 (BA0, BA1) 512 (A0–A8) 256 (A0–A7) Part Number Example: MT48V8M16LFB4-8:G ©2001 Micron Technology, Inc. All rights reserved. Mark LC V 8M16 4M32 -75M -8 3 -10 None ...

Page 2

Table of Contents FBGA Part Marking Decoder ...

Page 3

List of Figures Figure 2: Functional Block Diagram 8 Meg x 16 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 4

Figure 58: 90-Ball FBGA, “F5/B5” Package (x32 Device), 8mm x 13mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 5

List of Tables Table 1: Key Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 6

... General Description The Micron memory containing 134,217,728 bits internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x16’s 33,554,432-bit banks is organized as 4,096 rows by 512 columns by 16 bits. Each of the x32’s 33,554,432-bit banks is organized as 4,096 rows by 256 columns by 32 bits. Read and write accesses to the SDRAM are burst oriented ...

Page 7

... The 128Mb SDRAM device is designed to operate in 3.3V or 2.5V low-power memory systems. The 2.5V version is compatible with 1.8V I/O interface. An auto refresh mode is provided along with a power-saving, power-down mode. All inputs and outputs are LVTTL-compatible ...

Page 8

... WRITE DRIVERS LOGIC 2 COLUMN- 9 ADDRESS 9 COUNTER/ LATCH 8 128Mb: x16, x32 Mobile SDRAM General Description BANK3 BANK2 BANK1 BANK0 MEMORY 2 ARRAY DATA OUTPUT 16 REGISTER 4,096 DATA 16 INPUT 512 REGISTER (x16) COLUMN DECODER Micron Technology, Inc., reserves the right to change products or specifications without notice. ...

Page 9

... WRITE DRIVERS LOGIC 2 COLUMN- 8 ADDRESS 8 COUNTER/ LATCH 9 128Mb: x16, x32 Mobile SDRAM General Description BANK3 BANK2 BANK1 BANK0 MEMORY 4 ARRAY DATA OUTPUT 32 REGISTER 4096 DATA 32 INPUT 256 REGISTER (x32) COLUMN DECODER Micron Technology, Inc., reserves the right to change products or specifications without notice. ...

Page 10

Pin/Ball Assignments and Descriptions Figure 4: 90-Ball FBGA Pin Assignments (Top View) A DQ26 B DQ28 DQM1 DQ11 R DQ13 PDF: 09005aef807f4885/Source: ...

Page 11

Figure 5: 54-Pin TSOP Pin Assignments (Top View) x16 V DD DQ0 DQ1 DQ2 VssQ DQ3 DQ4 DQ5 DQ6 VssQ DQ7 V DD DQML WE# CAS# RAS# CS# BA0 BA1 A10 ...

Page 12

... A0–A11) and READ/WRITE command (column-address A0–A8; with A10 defining auto precharge) to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine whether all banks are to be precharged (A10 HIGH) or bank selected by BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD MODE REGISTER command ...

Page 13

... A0–A11) and READ/WRITE command (column-address A0–A7; with A10 defining auto precharge) to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine whether all banks are to be precharged (A10 HIGH) or bank selected by BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD MODE REGISTER command ...

Page 14

... A0–A11) and READ/WRITE command (column-address A0–A7; with A10 defining auto precharge) to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine whether all banks are to be precharged (A10 HIGH) or bank selected by BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD MODE REGISTER command ...

Page 15

Functional Description In general, the 128Mb SDRAMs (2 Meg banks and 1 Meg banks) are quad- bank DRAMs that operate at 3.3V or 2.5V and include a synchronous interface (all signals are ...

Page 16

Wait at least given. All banks will complete their precharge, thereby placing the device in the all banks idle state. 8. Issue an AUTO REFRESH command. 9. Wait at least are allowed. 10. Issue an AUTO REFRESH command. 11. ...

Page 17

The mode register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation. Burst Length (BL) Read and write ...

Page 18

Figure 7: Mode Register Definition M13 M12 Mode Register Definition 0 0 Program Mode Register 0 1 Program Extended Mode Register M11 M10 Valid – – – M9 Write Burst Mode 0 Programmed Burst Length 0 Single ...

Page 19

Table 6: Burst Definition Burst Length Full page (y) NOTE: Notes: 1. For full-page accesses 512 (x16 256 (x32). 2. For A1–A8 (x16) or A1–A7 (x32) select the block-of-two burst; A0 selects the ...

Page 20

DQ will start driving after T1, and the data will be valid by T2, as shown in Figure 8. Table 7 indicates the operating frequencies at which each CL setting can be used. ...

Page 21

Operating Mode The normal operating mode is selected by setting M7, M8, M10, and M11 to zero; all the other combinations of values for M7, M8, M10, and M11 are reserved for future use and/ or test modes. Test modes ...

Page 22

... Partial-Array Self Refresh (PASR) For further power savings during self refresh, the PASR feature allows the controller to select the amount of memory that will be refreshed during self refresh. The refresh options are all banks (banks and 3); two banks (banks 0 and 1); and one bank (bank 0). WRITE and READ commands occur to any bank selected during standard operation, but only the selected banks in PASR will be refreshed during self refresh. It’ ...

Page 23

Commands Table 8 provides a quick reference of available commands. This is followed by a written description of each command. Three additional Truth Tables appear following the Oper- ation section; these tables provide current state/next state information. Table 8: Truth ...

Page 24

... DQM input logic level appearing coincident with the data given DQM signal is registered LOW, the corresponding data will be written to memory; if the DQM signal is registered HIGH, the corresponding data inputs will be ignored, and a write will not be executed to that byte/column location. ...

Page 25

READ or WRITE burst, except in the full-page burst mode where auto precharge does not apply. Auto precharge is nonpersis- tent in that it is either enabled or disabled for each individual read or ...

Page 26

Upon exiting the self refresh mode, AUTO REFRESH commands must be issued every 15.625µs or less because both SELF REFRESH and AUTO REFRESH utilize the row refresh counter. Self refresh is not supported on automotive temperature (AT) devices. Operation BANK/ROW ...

Page 27

Figure 11: Example: Meeting CLK COMMAND READs READ bursts are initiated with a READ command, as shown in Figure 12. The starting column and bank addresses are provided with the READ command, and auto precharge is either enabled or disabled ...

Page 28

Upon completion of a burst, assuming no other commands have been initiated, the DQ will go High-Z. A full-page burst will continue until terminated. (At the end of the page, it will wrap to column 0 and continue.) Data from ...

Page 29

Figure 14: Consecutive READ Bursts CLK COMMAND ADDRESS CLK COMMAND ADDRESS CLK COMMAND ADDRESS Notes: 1. Each READ command may be to either bank. DQM is LOW. Shown with PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 ...

Page 30

Figure 15: Random READ Accesses CLK COMMAND ADDRESS CLK COMMAND ADDRESS CLK COMMAND ADDRESS Notes: 1. Each READ command may be to either bank. DQM is LOW full page (if BL > ...

Page 31

Figure 16: READ-to-WRITE CLK DQM COMMAND ADDRESS Notes used for illustration. 2. The READ command may be to any bank, and the WRITE command may be to any bank burst of 1 ...

Page 32

A fixed-length READ burst may be followed by, or truncated with, a PRECHARGE command to the same bank (provided that auto precharge was not activated), and a full- page burst may be truncated with a PRECHARGE command to the same ...

Page 33

Figure 18: READ-to-PRECHARGE CLK COMMAND ADDRESS CLK COMMAND ADDRESS COMMAND ADDRESS Notes: 1. Assumes either the last data element the last desired data element of a longer burst. 3. ...

Page 34

Figure 19: Terminating a READ Burst CLK COMMAND ADDRESS CLK COMMAND ADDRESS COMMAND ADDRESS Notes: 1. Page remains open after a BURST TERMINATE command either the last data element the ...

Page 35

WRITEs WRITE bursts are initiated with a WRITE command, as shown in Figure 20. The starting column and bank addresses are provided with the WRITE command, and auto precharge either is enabled or disabled for that access. If auto precharge ...

Page 36

Figure 21: WRITE Burst CLK COMMAND ADDRESS Notes DQM is LOW. Figure 22: WRITE-to-WRITE COMMAND ADDRESS TRANSITIONING DATA Notes: 1. DQM is LOW. Each WRITE command may be to any bank. Data for any WRITE burst ...

Page 37

In the case of a fixed-length burst being executed to completion, a PRECHARGE command issued at the optimum time (as described above) provides the same operation that would result from the same fixed-length burst with auto precharge. The disadvan- tage ...

Page 38

Figure 25: WRITE-to-PRECHARGE CLK t t WR@ DQM COMMAND ADDRESS t t WR@ DQM COMMAND ADDRESS Notes: 1. DQM could remain LOW in this example if the WRITE burst is a fixed length of two. Fixed-length or full-page WRITE bursts ...

Page 39

Figure 27: PRECHARGE Command CLK CKE CS# RAS# CAS# WE# A0-A9 A10 BA0, BA1 PRECHARGE The PRECHARGE command (see Figure 27) is used to deactivate the open row in a particular bank or the open row in all banks. The ...

Page 40

Figure 28: Power-Down CLK CKE COMMAND All banks idle CLOCK SUSPEND The clock suspend mode occurs when a column access/burst is in progress and CKE is registered low. In the clock suspend mode, the internal clock is deactivated, “freezing” the ...

Page 41

Burst Read/Single Write The burst read/single write mode is entered by programming the write burst mode bit (M9) in the mode register to a logic 1. In this mode, all WRITE commands result in the access of a single column ...

Page 42

Figure 31: READ With Auto Precharge Interrupted by a READ CLK COMMAND BANK n Internal States BANK m ADDRESS DQ Notes: 1. DQM is LOW greater, and Figure 32: READ With Auto Precharge ...

Page 43

Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will interrupt a WRITE on bank n when registered. The precharge to bank n will begin after valid data WRITE to bank n will be ...

Page 44

Table 9: Truth Table – CKE Notes 1–4 apply to entire table CKE CKE Current State Power-down Self refresh Clock suspend L H Power-down Self refresh Clock suspend H L All banks idle All ...

Page 45

Table 10: Truth Table – Current State Bank n, Command to Bank n Notes 1–6 apply to entire table; notes appear below table Current State CS# RAS# CAS# WE# Command (Action) Any Idle L ...

Page 46

The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must be applied on each positive clock edge during these states. Refreshing starts with registration of an AUTO REFRESH command and ends when ...

Page 47

Table 11: Truth Table – CURRENT STATE BANK n, COMMAND tO BANK m Notes 1–6 apply to entire table; notes appear below and on next page Current State CS# RAS# Any Idle X X Row L ...

Page 48

All states and sequences not shown are illegal or reserved. 7. READs or WRITEs to bank m listed in the Command (Action) column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled. ...

Page 49

Electrical Specifications Stresses greater than those listed in Table 12 may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the ...

Page 50

Table 13: Temperature Limits Parameter Operating case temperature: Commercial Industrial Automotive Junction temperature: Commercial Industrial Automotive Ambient temperature: Commercial Industrial Automotive Peak reflow temperature Notes: 1. MAX operating case temperature, T side of the device, as shown in Figures 35, ...

Page 51

Figure 35: Example Temperature Test Point Location, 54-Pin TSOP: Top View Test point Figure 36: Example Temperature Test Point Location, 54-Ball VFBGA: Top View Test point Figure 37: Example Temperature Test Point Location, 90-Ball VFBGA: Top View Test point PDF: ...

Page 52

Table 15: DC Electrical Characteristics and Operating Conditions (LC Version) Notes 1, 6 apply to entire table; notes appear on page 57; V Parameter/Condition Supply voltage I/O supply voltage Input high voltage: Logic 1; All inputs Input low voltage: Logic ...

Page 53

Table 17: Electrical Characteristics and Recommended AC Operating Conditions Notes apply to entire table; notes appear on page 57 Ac Characteristics Parameter Access time from CLK (positive edge) Address hold time Address setup time ...

Page 54

Table 18: AC Functional Characteristics Notes apply to entire table; notes appear on page 57 Parameter READ/WRITE command to READ/WRITE command CKE to clock disable or power-down entry mode CKE to clock enable or ...

Page 55

Table 19: I Specifications and Conditions (x16) DD Notes 11, 13, 31 apply to entire table; notes appear on page 57 2.5V ±0. Parameter/Condition Operating current: Active mode; Burst = ...

Page 56

Table 21: I Specifications And Conditions (x32) DD Notes 11, 13, 31 apply to entire table; notes appear on page 57 2.5V ±0. Parameter/Condition Operating current: Active mode; Burst = ...

Page 57

Notes 1. All voltages are referenced to Vss. 2. This parameter is sampled. V 1.4V MHz with minimum cycle time and the outputs open. 4. Enables on-chip refresh and address counters. 5. The minimum ...

Page 58

V IH cannot be greater than one-third of the cycle rate pulse width ≤ 3ns and cannot be greater than one-third of the cycle rate. 23. The clock frequency must remain constant (stable clock is defined as ...

Page 59

Timing Diagrams Figure 38: Initialize and Load Mode Register CLK ( ( ) ) CKS CKH ( ( ) ) CKE ( ( ) ) t t CMS CMH ( ( ...

Page 60

Figure 39: Power-down Mode T0 CLK CKE t CKS t CKH t CMS t CMH COMMAND PRECHARGE DQML, DQMU A0–A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK(S) High-Z DQ Precharge all ...

Page 61

Figure 40: Clock Suspend Mode CLK CKS t CKH CKE t CKS t CKH t CMS t CMH 1 COMMAND READ NOP t CMS t CMH DQMU, DQML ...

Page 62

Figure 41: Auto Refresh Mode T0 CLK t CK CKE t CKS t CKH t CMS t CMH COMMAND PRECHARGE DQMU, DQML A0–A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK(S) High-Z DQ Precharge all ...

Page 63

Figure 42: Self Refresh Mode T0 CLK t CK CKE t CKS t CKH t CMS t CMH COMMAND PRECHARGE DQMU, DQML A0–A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK(S) High-Z DQ Precharge all ...

Page 64

Figure 43: READ – Without Auto Precharge T0 T1 CLK CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQMU, DQML A0–A9, A11 ROW ROW A10 DISABLE ...

Page 65

Figure 44: Read – With Auto Precharge T0 T1 CLK CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQMU, DQML A0–A9, A11 ROW ENABLE AUTO PRECHARGE ...

Page 66

Figure 45: Single Read – Without Auto Precharge T0 T1 CLK CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQMU, DQML A0–A9, A11 ROW ROW A10 ...

Page 67

Figure 46: Single Read – With Auto Precharge T0 T1 CLK CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQMU, DQML A0–A9, A11 ROW ROW A10 ...

Page 68

Figure 47: Alternating Bank Read Accesses T0 T1 CLK CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQMU, DQML A0–A9, A11 ROW ENABLE AUTO PRECHARGE ROW ...

Page 69

Figure 48: Read – Full-Page Burst CLK CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS DQMU, DQML COLUMN m 2 A0–A9, A11 ROW t ...

Page 70

Figure 49: Read – DQM Operation T0 T1 CLK CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQMU, DQML A0–A9, A11 ROW ENABLE AUTO PRECHARGE ROW ...

Page 71

Figure 50: Write – Without Auto Precharge CLK CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS DQMU, DQML A0–A9, A11 COLUMN m 3 ROW ...

Page 72

Figure 51: Write – With Auto Precharge CLK CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS DQMU, DQML COLUMN m 2 A0–A9, A11 ROW ...

Page 73

Figure 52: Single Write – Without Auto Precharge T0 T1 CLK CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQMU, DQML A0–A9, A11 ROW ROW A10 ...

Page 74

Figure 53: Single Write – With Auto Precharge CLK CKS t CKH CKE t CMS t CMH NOP 3 COMMAND ACTIVE DQMU, DQML A0–A9, A11 ROW ...

Page 75

Figure 54: Alternating Bank Write Accesses CLK CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS DQMU, DQML A0–A9, A11 ROW ...

Page 76

Figure 55: Write – Full-page Burst T0 T1 CLK CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQMU, DQML A0–A9, A11 ROW ROW A10 t AS ...

Page 77

Figure 56: Write – DQM Operation T0 CLK CKS t CKH CKE t CMS t CMH COMMAND ACTIVE DQMU, DQML A0-A9, A11 ROW ROW A10 ...

Page 78

Package Dimensions Figure 57: 54-Ball FBGA, “F4/B4” Package (x16 Device), 8mm x 8mm 0.65 ±0.05 SEATING PLANE C 0.10 C 54X Ø0.45 ±0.05 SOLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION. THE PRE- REFLOW DIAMETER IS 0.42. BALL A9 6.40 ...

Page 79

Figure 58: 90-Ball FBGA, “F5/B5” Package (x32 Device), 8mm x 13mm 0.65 ±0.05 SEATING PLANE A 0.10 A 90X Ø0.45 DIMENSIONS APPLY TO SOLDER BALLS POST REFLOW. THE PRE- REFLOW DIAMETER IS 0. 0.40 SMD BALL PAD BALL ...

Page 80

Figure 59: 54-Pin Plastic TSOP (400 mil) 22.22 ±0.08 0.80 TYP 0.375 ±0.075 PIN #1 ID LEAD FINISH: TIN/LEAD PLATE PLASTIC PACKAGE MATERIAL: EPOXY NOVOLAC PACKAGE WIDTH AND LENGTH DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 PER SIDE. ...

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