MT48V8M16LFB4-8:G Micron Technology Inc, MT48V8M16LFB4-8:G Datasheet - Page 40

IC SDRAM 128MBIT 125MHZ 54VFBGA

MT48V8M16LFB4-8:G

Manufacturer Part Number
MT48V8M16LFB4-8:G
Description
IC SDRAM 128MBIT 125MHZ 54VFBGA
Manufacturer
Micron Technology Inc
Type
Mobile SDRAMr

Specifications of MT48V8M16LFB4-8:G

Format - Memory
RAM
Memory Type
Mobile SDRAM
Memory Size
128M (8Mx16)
Speed
125MHz
Interface
Parallel
Voltage - Supply
2.3 V ~ 2.7 V
Operating Temperature
0°C ~ 70°C
Package / Case
54-VFBGA
Organization
8Mx16
Density
128Mb
Address Bus
14b
Access Time (max)
19/8/7ns
Maximum Clock Rate
125MHz
Operating Supply Voltage (typ)
2.5V
Package Type
VFBGA
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.3V
Supply Current
100mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MT48V8M16LFB4-8:G
Manufacturer:
MICRON
Quantity:
4 000
Part Number:
MT48V8M16LFB4-8:G
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Part Number:
MT48V8M16LFB4-8:G TR
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Figure 28:
CLOCK SUSPEND
Figure 29:
PDF: 09005aef807f4885/Source: 09005aef8071a76b
128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN
Power-Down
Clock Suspend During WRITE Burst
Notes:
COMMAND
The clock suspend mode occurs when a column access/burst is in progress and CKE is
registered low. In the clock suspend mode, the internal clock is deactivated, “freezing”
the synchronous logic.
For each positive clock edge on which CKE is sampled LOW, the next internal positive
clock edge is suspended. Any command or data present on the input pins at the time of a
suspended internal clock edge is ignored; any data present on the DQ pins remains
driven; and burst counters are not incremented as long as the clock is suspended. (See
examples in Figure 29 and in Figure 30 on page 41.)
COMMAND
1. For this example, burst length = 4 or greater, and DM is LOW.
Clock suspend mode is exited by registering CKE HIGH; the internal clock and related
operation will resume on the subsequent positive clock edge.
INTERNAL
ADDRESS
CLOCK
All banks idle
CLK
CKE
CLK
CKE
D
Enter power-down mode.
IN
NOP
T0
t CKS
NOP
WRITE
BANK,
COL n
T1
D
n
IN
Input buffers gated off
TRANSITIONING DATA
T2
40
(
(
(
(
)
(
)
)
)
)
(
(
(
(
)
(
)
)
T3
)
)
Exit power-down mode.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
NOP
n + 1
T4
D
IN
128Mb: x16, x32 Mobile SDRAM
> t CKS
DON’T CARE
T5
NOP
n + 2
D
NOP
IN
DON’T CARE
©2001 Micron Technology, Inc. All rights reserved.
ACTIVE
t RCD
t RAS
t RC
READs

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