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MT48V8M16LFB4-8:G TR
MT48V8M16LFB4-8:G TR | |
|---|---|
| Manufacturer Part Number | MT48V8M16LFB4-8:G TR |
| Description | IC SDRAM 128MBIT 125MHZ 54VFBGA |
| Manufacturer | Micron Technology Inc |
| MT48V8M16LFB4-8:G TR datasheets |
|
Availability: By request
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Warranty: 60 days
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Specifications of MT48V8M16LFB4-8:G TR | |||
|---|---|---|---|
| Format - Memory | RAM | Memory Type | Mobile SDRAM |
| Memory Size | 128M (8Mx16) | Speed | 125MHz |
| Interface | Parallel | Voltage - Supply | 2.3 V ~ 2.7 V |
| Operating Temperature | 0°C ~ 70°C | Package / Case | 54-VFBGA |
| Lead Free Status / RoHS Status | Lead free / RoHS Compliant | ||
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Table 4:
Ball Descriptions: 90-Ball VFBGA
90-Ball FBGA
Symbol
J1
CLK
J2
CKE
J8
CS#
J9, K7, K8
RAS#, CAS#,
WE#
K9, K1, F8, F2
DQM0–3
J7, H8
BA0, BA1
G8, G9, F7, F3, G1, G2,
A0–A5
G3, H1, H2, J3, G7, H9
A6–A11
R8, N7, R9, N8, P9, M8,
DQ0–DQ5
M7, L8, L2, M3, M2, P1,
DQ6–DQ11
N2, R1, N3, R2, E8, D7,
DQ12–DQ17
D8, B9, C8, A9, C7, A8,
DQ18–DQ23
A2, C3, A1, C2, B1, D2,
DQ24–DQ29
D3, E2
DQ30–DQ31
E3, E7, H3, H7, K2, K3
NC
B2, B7, C9, D9, E1, L1,
V
Q
DD
M9, N9, P2, P7
B8, B3, C1, D1, E9, L9,
V
Q
SS
M1, N1, P3, P8
A7, F9, L7, R7
V
DD
A3, F1, L3, R3
V
SS
PDF: 09005aef807f4885/Source: 09005aef8071a76b
128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN
Pin/Ball Assignments and Descriptions
Type
Description
Input
Clock: CLK is driven by the system clock. All SDRAM input signals are
sampled on the positive edge of CLK. CLK also increments the internal
burst counter and controls the output registers.
Input
Clock enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal.
Deactivating the clock provides precharge power-down and SELF
REFRESH operation (all banks idle), active power-down (row active in any
bank), or CLOCK SUSPEND operation (burst/access in progress). CKE is
synchronous except after the device enters power-down and self refresh
modes, where CKE becomes asynchronous until after exiting the same
mode. The input buffers, including CLK, are disabled during power-down
and self refresh modes, providing low standby power. CKE may be tied
HIGH.
Input
Chip select: CS# enables (registered LOW) and disables (registered HIGH)
the command decoder. All commands are masked when CS# is registered
HIGH, but READ/WRITE bursts already in progress will continue and DQM
will retain its DQ mask capability while CS# remains HIGH. CS# provides
for external bank selection on systems with multiple banks. CS# is
considered part of the command code.
Input
Command inputs: RAS#, CAS#, and WE# (along with CS#) define the
command being entered.
Input
Input/Output mask: DQM is sampled HIGH and is an input mask signal for
write accesses and an output enable signal for read accesses. Input data is
masked during a WRITE cycle. The output buffers are placed in a High-Z
state (2-clock latency) during a READ cycle. DQM0 corresponds to DQ0–
DQ7, DQM1 corresponds to DQ8–DQ15, DQM2 corresponds to DQ16–
DQ23, and DQM3 corresponds to DQ24–DQ31. DQM0–3 are considered
same state when referenced as DQM.
Input
Bank address input(s): BA0 and BA1 define to which bank the ACTIVE,
READ, WRITE, or PRECHARGE command is being applied. These pins also
provide the op-code during a LOAD MODE REGISTER command.
Input
Address inputs: A0–A11 are sampled during the ACTIVE command (row-
address A0–A11) and READ/WRITE command (column-address A0–A7;
with A10 defining auto precharge) to select one location out of the
memory array in the respective bank. A10 is sampled during a
PRECHARGE command to determine whether all banks are to be
precharged (A10 HIGH) or bank selected by BA0, BA1 (LOW). The address
inputs also provide the op-code during a LOAD MODE REGISTER
command.
I/O
Data input/output: Data bus.
–
No connect: These pins should be left unconnected. H3 is a no connect
for this part, but may be used as A12 in future designs.
Supply DQ power: Isolated DQ power on the die to improve noise immunity.
Supply DQ ground: Isolated DQ power on the die to improve noise immunity.
Supply Power supply: Voltage dependant on option.
Supply Ground.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
13
128Mb: x16, x32 Mobile SDRAM
©2001 Micron Technology, Inc. All rights reserved.
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