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MT48V8M16LFB4-8:G TR
MT48V8M16LFB4-8:G TR | |
|---|---|
| Manufacturer Part Number | MT48V8M16LFB4-8:G TR |
| Description | IC SDRAM 128MBIT 125MHZ 54VFBGA |
| Manufacturer | Micron Technology Inc |
| MT48V8M16LFB4-8:G TR datasheets |
|
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Specifications of MT48V8M16LFB4-8:G TR | |||
|---|---|---|---|
| Format - Memory | RAM | Memory Type | Mobile SDRAM |
| Memory Size | 128M (8Mx16) | Speed | 125MHz |
| Interface | Parallel | Voltage - Supply | 2.3 V ~ 2.7 V |
| Operating Temperature | 0°C ~ 70°C | Package / Case | 54-VFBGA |
| Lead Free Status / RoHS Status | Lead free / RoHS Compliant | ||
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Table 9:
Truth Table – CKE
Notes 1–4 apply to entire table
CKE
CKE
Current State
n - 1
n
L
L
Power-down
Self refresh
Clock suspend
L
H
Power-down
Self refresh
Clock suspend
H
L
All banks idle
All banks idle
Reading or writing
H
H
Notes:
1. CKE
clock edge.
2. Current state is the state of the SDRAM immediately prior to clock edge n.
3. COMMAND
MAND
4. All states and sequences not shown are illegal or reserved.
5. Exiting power-down at clock edge n will put the device in the all banks idle state in time for
clock edge n + 1 (provided that
6. Exiting self refresh at clock edge n will put the device in the all banks idle state after
met. COMMAND INHIBIT or NOP commands should be issued on any clock edges occurring
during the
period.
7. After exiting clock suspend at clock edge n, the device will resume operation and recognize
the next command at clock edge n + 1.
PDF: 09005aef807f4885/Source: 09005aef8071a76b
128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN
Comand
n
X
X
X
COMMAND INHIBIT or NOP
COMMAND INHIBIT or NOP
X
COMMAND INHIBIT or NOP
AUTO REFRESH
WRITE or NOP
See Table 10 on page 45
is the logic state of CKE at clock edge n; CKE
n
is the command registered at clock edge n, and ACTION
n
.
n
t
CKS is met).
t
XSR period. A minimum of two NOP commands must be provided during
44
128Mb: x16, x32 Mobile SDRAM
Action
Maintain power-down
Maintain self refresh
Maintain clock suspend
Exit power-down
Exit self refresh
Exit clock suspend
Power-down entry
self refresh entry
Clock suspend entry
was the state of CKE at the previous
n - 1
is a result of COM-
n
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001 Micron Technology, Inc. All rights reserved.
READs
Notes
5
6
7
t
XSR is
t
XSR
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