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MT48V8M16LFB4-8:G TR
MT48V8M16LFB4-8:G TR | |
|---|---|
| Manufacturer Part Number | MT48V8M16LFB4-8:G TR |
| Description | IC SDRAM 128MBIT 125MHZ 54VFBGA |
| Manufacturer | Micron Technology Inc |
| MT48V8M16LFB4-8:G TR datasheets |
|
Availability: By request
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Warranty: 60 days
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Specifications of MT48V8M16LFB4-8:G TR | |||
|---|---|---|---|
| Format - Memory | RAM | Memory Type | Mobile SDRAM |
| Memory Size | 128M (8Mx16) | Speed | 125MHz |
| Interface | Parallel | Voltage - Supply | 2.3 V ~ 2.7 V |
| Operating Temperature | 0°C ~ 70°C | Package / Case | 54-VFBGA |
| Lead Free Status / RoHS Status | Lead free / RoHS Compliant | ||
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Notes
1. All voltages are referenced to Vss.
2. This parameter is sampled. V
1.4V, f = 1 MHz.
3. I
DD
with minimum cycle time and the outputs open.
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to indicate cycle time at which proper
operation over the full temperature range is ensured (0°C ≤ T
40°C ≤ T
6. An initial pause of 100µs is required after power-up, followed by two AUTO REFRESH
commands, before proper device operation is ensured. (V
ered up simultaneously. V
REFRESH command wake-ups should be repeated any time the
ment is exceeded.
7. AC characteristics assume
8. In addition to meeting the transition rate specification, the clock and CKE must tran-
sit between V
9. Outputs measured at 1.5V (for LC devices) or at 1.25V (V devices) with equivalent
load:
Q
t
10.
HZ defines the time at which the output achieves the open circuit condition; it is not
a reference to V
High-Z.
11. AC timing and I
to V
ing is referenced at V
Established tester values follow: V
devices.
12. Other input signals are allowed to transition no more than once every 2 clocks and are
otherwise at valid V
13. I
DD
14. Timing actually specified by
cycle rate.
15. Timing actually specified by
minimum cycle rate.
16. Timing actually specified by
17. Required clocks are specified by JEDEC functionality and are not dependent on any
timing parameter.
18. The I
frequency alteration for the test condition.
19. Address transitions average one transition every 2 clocks.
20. CLK must be toggled a minimum of two times during this period.
21. Based on
PDF: 09005aef807f4885/Source: 09005aef8071a76b
128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN
, V
DD
DD
is dependent on output loading and cycle rates. Specified values are obtained
+85°C (industrial), and –40°C ≤ T
≤
A
and V
Q must be at same potential.) The two AUTO
SS
SS
t
T = 1ns.
and V
(or between V
IH
IL
30pF
or V
. The last valid data element will meet
OH
OL
tests use established values for V
DD
/2 crossover point. If the input transition time is longer than 1ns, then the tim-
IH
(
) and V
IL
MAX
IH
= 0V, V
IL
or V
levels.
IH
IL
specifications are tested after the device is properly initialized.
t
CKS; clock(s) specified as a reference only at minimum
t
WR plus
t
WR.
current will increase or decrease proportionally according to the amount of
DD
t
t
CK = 125MHz for -8 and
CK = 100MHz for -10.
57
128Mb: x16, x32 Mobile SDRAM
Q = +3.3V; T
= 25°C; pin under test biased at
A
≤
+70°C (commercial), –
A
≤
+105°C (automotive)).
A
and V
DD
DD
t
REF refresh require-
and V
) in a monotonic manner.
IL
IH
t
OH before going
and V
, with timing referenced
IL
IH
(
) and no longer at the V
/2 crossover point.
MIN
IH
= 3.0V for LC devices and V
IH
t
RP; clock(s) specified as a reference only at
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001 Micron Technology, Inc. All rights reserved.
Notes
Q must be pow-
= 2.3V for V
IH
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