IC SDRAM 128MBIT 125MHZ 54VFBGA

 

MT48V8M16LFB4-8:G TR

Manufacturer Part NumberMT48V8M16LFB4-8:G TR
DescriptionIC SDRAM 128MBIT 125MHZ 54VFBGA
ManufacturerMicron Technology Inc
MT48V8M16LFB4-8:G TR datasheets

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Specifications of MT48V8M16LFB4-8:G TR

Format - MemoryRAMMemory TypeMobile SDRAM
Memory Size128M (8Mx16)Speed125MHz
InterfaceParallelVoltage - Supply2.3 V ~ 2.7 V
Operating Temperature0°C ~ 70°CPackage / Case54-VFBGA
Lead Free Status / RoHS StatusLead free / RoHS Compliant  
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22. V
IH
cannot be greater than one-third of the cycle rate. V
a pulse width ≤ 3ns and cannot be greater than one-third of the cycle rate.
23. The clock frequency must remain constant (stable clock is defined as a signal cycling
within timing constraints specified for the clock pin) during access or precharge
states (READ, WRITE, including
used to reduce the data rate.
24. Auto precharge mode only. The precharge timing budget (
after the first clock delay after the last WRITE is executed.
25. Manual precharge mode only.
26. JEDEC and PC100 specify 3 clocks.
27. Parameter guaranteed by design.
28. PC100 specifies a maximum of 4pF.
29. PC100 specifies a maximum of 5pF.
30. PC100 specifies a maximum of 6.5pF.
31. For -75M, CL = 3 and
t
CK = 10ns.
32. CKE is HIGH during refresh command period
limit is actually a nominal value and does not result in a fail value.
33. Specified with I/Os in steady state condition.
PDF: 09005aef807f4885/Source: 09005aef8071a76b
128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN
Q + 2V for a pulse width ≤ 3ns, and the pulse width
overshoot: V
(MAX) = V
IH
DD
t
WR, and PRECHARGE commands). CKE may be
t
CK = 7.5ns; for -8, CL = 3 and
58
128Mb: x16, x32 Mobile SDRAM
undershoot: V
IL
IL
t
RP) begins at 5.4ns for -8
t
CK = 8ns; for -10, CL = 3 and
t
RFC (MIN) else CKE is LOW. The I
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001 Micron Technology, Inc. All rights reserved.
Notes
(MIN) = –2V for
6
DD