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MT48V8M16LFB4-8:G TR
MT48V8M16LFB4-8:G TR | |
|---|---|
| Manufacturer Part Number | MT48V8M16LFB4-8:G TR |
| Description | IC SDRAM 128MBIT 125MHZ 54VFBGA |
| Manufacturer | Micron Technology Inc |
| MT48V8M16LFB4-8:G TR datasheets |
|
Availability: By request
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Warranty: 60 days
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Specifications of MT48V8M16LFB4-8:G TR | |||
|---|---|---|---|
| Format - Memory | RAM | Memory Type | Mobile SDRAM |
| Memory Size | 128M (8Mx16) | Speed | 125MHz |
| Interface | Parallel | Voltage - Supply | 2.3 V ~ 2.7 V |
| Operating Temperature | 0°C ~ 70°C | Package / Case | 54-VFBGA |
| Lead Free Status / RoHS Status | Lead free / RoHS Compliant | ||
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Figure 52:
Single Write – Without Auto Precharge
T0
T1
CLK
t CK
t CKS
t CKH
CKE
t CMS
t CMH
COMMAND
ACTIVE
NOP
DQMU, DQML
t AS
t AH
A0–A9, A11
ROW
t AS
t AH
ROW
A10
DISABLE AUTO PRECHARGE
t AS
t AH
BA0, BA1
BANK
DQ
t RCD
t RAS
t RC
Notes:
1. For this example, BL = 1, and the WRITE burst is followed by a “manual” PRECHARGE.
2. 15ns is required between <D
3. x16: A9 and A11 = “Don’t Care.”
x32: A8, A9, and A11 = “Don’t Care.”
4. PRECHARGE command not allowed or
See Table 17 on page 53.
PDF: 09005aef807f4885/Source: 09005aef8071a76b
128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN
T2
T3
T4
t CL
t CH
NOP 4
NOP 4
WRITE
t CMS
t CMH
COLUMN m 3
BANK
t DS
t DH
D
m
IN
t WR
2
m> and the PRECHARGE command regardless of frequency.
IN
t
Micron Technology, Inc., reserves the right to change products or specifications without notice.
73
128Mb: x16, x32 Mobile SDRAM
Timing Diagrams
T5
T6
T7
PRECHARGE
NOP
ACTIVE
ALL BANKS
ROW
SINGLE BANK
BANK
BANK
t RP
RAS would be violated.
©2001 Micron Technology, Inc. All rights reserved.
T8
NOP
DON’T CARE
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