MT45W4MW16BCGB-701 IT Micron Technology Inc, MT45W4MW16BCGB-701 IT Datasheet
MT45W4MW16BCGB-701 IT
Specifications of MT45W4MW16BCGB-701 IT
Related parts for MT45W4MW16BCGB-701 IT
MT45W4MW16BCGB-701 IT Summary of contents
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... A19 A12 A13 WE# DQ7 H A18 A8 A9 A10 A11 A20 J WAIT CLK ADV# RFU RFU RFU Top view (Ball down) Designator quency exceed the CellularRAM 1.5 Work- group specification. Part Number Example: MT45W4MW16BCGB-701LWT ©2005 Micron Technology, Inc. All rights reserved. Features None ...
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... Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Timing Requirements .38 Timing Diagrams .42 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhzTOC.fm - Rev. F 9/07 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. 2 Table of Contents ©2005 Micron Technology, Inc. All rights reserved. ...
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... Figure 54: Asynchronous WRITE Followed by Asynchronous READ – ADV# LOW . . . . . . . . . . . . . . . . . . . . . . . .67 Figure 56: 54-Ball VFBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhzLOF.fm - Rev. F 9/07 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 TCR Micron Technology, Inc., reserves the right to change products or specifications without notice. 3 List of Figures ©2005 Micron Technology, Inc. All rights reserved. ...
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... Burst WRITE Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Table 20: Initialization Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhzLOT.fm - Rev. F 9/07 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. 4 List of Tables ©2005 Micron Technology, Inc. All rights reserved. ...
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... General Description Micron low-power, portable applications. The MT45W4MW16BCGB is a 64Mb DRAM core device, organized as 4 Meg x 16 bits. This device includes an industry-standard burst mode Flash interface that dramatically increases read/write bandwidth compared with other low-power SRAM or pseudo-SRAM (PSRAM) offerings. For seamless operation on a burst Flash bus, CellularRAM products incorporate a trans- parent self refresh mechanism ...
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... Table 1 on page 7; bus operations in Table 2 on page 8, Table 3 on page 9, and Table 2 on page 8; and timing diagrams starting on page 42. PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Address decode 4,096K x 16 logic ...
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... Output enable: Enables the output buffers when LOW. When OE# is HIGH, the output buffers are disabled. Write enable: Determines whether a given cycle is a WRITE cycle. If WE# is LOW, the cycle is a WRITE either to a configuration register or to the memory array. Lower byte enable. DQ[7:0] Upper byte enable. DQ[15:8] Data inputs/outputs ...
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... The WAIT polarity is configured through the bus configuration register (BCR[10]). 3. When LB# and UB# are in select mode (LOW), DQ[15:0] are enabled. When only LB select mode, DQ[7:0] are enabled. When only UB the select mode, DQ[15:8] are enabled. PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory 1 CLK ADV# CE# OE# ...
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... Burst mode operation is initialized through the bus configuration register (BCR[15]). 9. Initial cycle. Following cycles are the same as BURST CONTINUE. CE# must stay LOW for the equivalent of a single-word burst (as indicated by WAIT). PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory 1 CLK ADV# CE# ...
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... CSN-11, “Product Mark/ Label,” at www.micron.com/support/designsupport/documents/csn. PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory BC GB -70 8 Package Codes GB = 54-ball VFBGA “green” grid, 0.75mm pitch, 6.0mm x 8.0mm x 1.0mm) www ...
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... Functional Description In general, the MT45W4MW16BCGB device is a high-density alternative to SRAM and PSRAM products, popular in low-power, portable applications. The MT45W4MW16BCGB contains a 67,108,864-bit DRAM core, organized as 4,194,304 addresses by 16 bits. The device implements the same high-speed bus interface found on burst mode Flash products. ...
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... WRITE Operation (ADV# LOW) CE# OE# WE# Address Data LB#/UB# PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Valid address Valid data READ cycle time < t CEM Valid address Valid data WRITE cycle time Don’t Care Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... CellularRAM device. The initial latency for READ operations can be configured as fixed or variable PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory < t CEM Add[0] Add[1] Add[2] Add[3] ...
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... Fixed latency also provides improved performance at lower clock frequencies. The WAIT output asserts when a burst is initiated and de-asserts to indicate when data transferred into or out of memory. WAIT will again be asserted at the boundary of the 128-word row, unless wrapping within the burst length. To access other devices on the same bus without the timing penalty of the initial latency for a new burst, burst mode can be suspended ...
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... LOW during the entire WRITE operation. CE# can remain LOW when transi- tioning between mixed-mode operations with fixed latency enabled; however, the CE# LOW time must not exceed to legacy burst mode Flash memory controllers. See Figure 50 on page 63 for the “Asyn- chronous WRITE Followed by Burst READ” timing diagram. WAIT Operation The WAIT output on a CellularRAM device typically is connected to a shared, system- level WAIT signal (see Figure 10 on page 16) ...
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... CellularRAM device requires additional time before data can be transferred. For READ operations, WAIT will remain active until valid data is output from the device. For WRITE operations, WAIT will indicate to the memory controller when data will be accepted into the CellularRAM device. When WAIT transitions to an inactive state, the data burst will progress on successive clock edges ...
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... Nondefault BCR settings for refresh collision during variable-latency READ operation: latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during delay. PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. 17 Bus Operating Modes ...
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... Partial-array refresh (PAR) restricts refresh operation to a portion of the total memory array. This feature enables the device to reduce standby current by refreshing only that part of the memory array required by the host system. The refresh options are full array, one-half array, one-quarter array, one-eighth array, or none of the array. The mapping of these partitions can start either at the beginning or the end of the address map (see Table 8 on page 32) ...
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... The registers can be accessed either using a synchronous or an asynchronous operation when the control register enable (CRE) input is HIGH (see Figures 12 through 15). When CRE is LOW, a READ or WRITE operation will access the memory array. The configura- tion register values are written via addresses A[21:0 asynchronous WRITE, the values are latched into the configuration register on the rising edge of ADV#, CE#, or WE#, whichever occurs first ...
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... WAIT cycles caused by refresh collisions require a corresponding number of addi- tional CE# LOW cycles. PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Latch control register address Note 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... A[19:18] CRE t VPH ADV# CE# OE# WE# LB#/UB# DQ[15:0] Notes: 1. A[19:18] = 00b to read RCR, 10b to read BCR, and 01b to read DIDR. PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory t AVH t AVS AVH t AVS AAVD Initiate register access OLZ ...
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... CE# must remain LOW to complete a burst-of-one READ. WAIT must be monitored—addi- tional WAIT cycles caused by refresh collisions require a corresponding number of addi- tional CE# LOW cycles. PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Latch control register address ABA ...
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... CRE can simply be tied to V purposes is no longer required. Figure 16: Load Configuration Register Address CE# OE# WE# LB#/UB# Data PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory READ READ WRITE Address Address Address (MAX) (MAX) (MAX) XXXXh XXXXh ...
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... Figure 17: Read Configuration Register Address CE# OE# WE# LB#/UB# Data PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory READ READ WRITE Address Address Address (MAX) (MAX) (MAX) XXXXh XXXXh RCR: 0000h BCR: 0001h DIDR: 0002h Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... Bus Configuration Register The BCR defines how the CellularRAM device interacts with the system memory bus. Page mode operation is enabled by a bit contained in the RCR. Figure 18 defines the control bits in the BCR. At power-up, the BCR is set to 9D1Fh. The BCR is accessed with CRE HIGH and A[19:18] = 10b or through the register access software sequence with DQ = 0001h on the third cycle ...
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... ... 14 15 ... 30 31 PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory 8-Word 16-Word Burst Length Burst Length Linear Linear 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15 1-2-3-4-5-6-7-0 1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-0 2-3-4-5-6-7-0-1 2-3-4-5-6-7-8-9-10-11-12-13-14-15-0-1 3-4-5-6-7-0-1-2 3-4-5-6-7-8-9-10-11-12-13-14-15-0-1-2 4-5-6-7-0-1-2-3 4-5-6-7-8-9-10-11-12-13-14-15-0-1-2-3 5-6-7-0-1-2-3-4 5-6-7-8-9-10-11-12-13-14-15-0-1-2-3-4 6-7-0-1-2-3-4-5 6-7-8-9-10-11-12-13-14-15-0-1-2-3-4-5 ...
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... The WAIT configuration bit is used to determine when WAIT transitions between the asserted and the de-asserted state with respect to valid data presented on the data bus. The memory controller will use the WAIT signal to coordinate data transfer during synchronous READ and WRITE operations. When BCR[ data will be valid or invalid on the clock edge immediately after WAIT transitions to the de-asserted or asserted state, respectively (see Figures 19 and 21) ...
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... Operating Mode (BCR[15]) Default = Asynchronous Operation The operating mode bit either selects synchronous burst operation or the default asyn- chronous mode of operation. PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory High-Z Data 0 D[0] D[1] Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... V IH Valid A[21:0] address ADV DQ[15: DQ[15: PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory 1 Latency Normal Refresh Collision – – Code 2 Valid output Code 3 (Default) 29 Maximum Input CLK Frequency (MHz) -7013 -701 66 (15.0ns) 66 (15.0ns) 104 (9.62ns) 104 (9 ...
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... CE DQ[15: (READ DQ[15: (WRITE) Burst identified (ADV# = LOW) PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Latency Count ( 104 (9.62ns) 8 – N-1 Cycles Cycle AADV ACLK Valid output Valid input Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... DQ = 0000h on the third cycle (see “Registers” on page 18). Partial-Array Refresh (RCR[2:0]) Default = Full Array Refresh The PAR bits restrict refresh operation to a portion of the total memory array. This feature allows the device to reduce standby current by refreshing only that part of the memory array required by the host system ...
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... The page mode operation bit determines whether page mode is enabled for asynchro- nous READ operations. In the power-up default state, page mode is disabled. PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Active Section Address Space Full die 000000h– ...
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... Bit setting 128 words Meaning Note: Vendors with 256-word row lengths for CellularRAM 1.5 devices will set DIDR[15] to 1b. PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory DIDR[14:11] DIDR[10:8] Device version Device density Bit Setting Version 010b ...
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... Exposure to absolute maximum rating conditions for extended periods may affect reli- ability. PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Q supply relative to V –0.5V to (4. ...
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... V for up to 500ms after power-up or when entering standby mode characterization and is not 100 percent tested. PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory < +85ºC); Industrial temperature (–40ºC < Conditions Symbol V CC ...
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... Table 14: Deep Power-Down Specifications Description Deep power-down Note PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Symbol I Standard power PAR (no designation) Low-power option (L) (MAX) values are measured at 85° TCR 10 20 ...
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... Figure 27: AC Output Load Circuit DUT Note: All tests are performed with the outputs configured for a default setting of half drive strength (BCR[5:4] = 01b). PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Conditions Symbol T = +25° MHz ...
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... High-Z to Low-Z timings are tested with the circuit shown in Figure 27 on page 37. The Low-Z timings measure a 100mV transition away from the High-Z (V toward V 3. Page mode enabled only. PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Symbol AADV ...
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... High-Z to Low-Z timings are tested with the circuit shown in Figure 27 on page 37. The Low-Z timings measure a 100mV transition away from the High-Z (V toward V PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory -7013 (133 MHz) Symbol Min ...
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... High-Z to Low-Z timings are tested with the circuit shown in Figure 27 on page 37. The Low-Z timings measure a 100mV transition away from the High-Z (V toward V 3. WE# LOW time must be limited to PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Symbol AVH ...
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... CE# HIGH or b) CE# HIGH for longer than 15ns. 3. Low-Z to High-Z timings are tested with the circuit shown in Figure 27 on page 37. The High-Z timings measure a 100mV transition either from V PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory -7013 (133 Mhz) Symbol Min Max ...
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... Initialization Timing Parameters Parameter Time from DPD entry to DPD exit CE# LOW time to exit DPD Initialization period Notes: 1. The CellularRAM Workgroup 1.5 specification for PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory DPD t DPDX DPD exit Symbol t DPD t ...
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... Figure 30: Asynchronous READ A[21:0] ADV# CE# LB#/UB# OE# WE# DQ[15:0] WAIT PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Valid address OLZ BLZ High CEW V IH High Don’t Care Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... Figure 31: Asynchronous READ Using ADV# A[21:0] ADV# CE# LB#/UB# OE# WE# DQ[15:0] WAIT PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory V IH Valid address VPH t AVS t AVH AADV CVS OLZ BLZ High CEW V IH High Don’t Care Micron Technology, Inc ...
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... Figure 32: Page Mode READ A[21:4] A[3:0] ADV# CE# LB#/UB# OE# WE# DQ[15:0] WAIT PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Valid address Valid Valid address address CEM OLZ BLZ t APA Valid High-Z Output CEW V OH High Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... Single-Access Burst READ Operation – Variable Latency CLK A[21:0] ADV# CE# OE# WE# LB#/UB# WAIT DQ[15:0] Note: Nondefault BCR settings: latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during delay. PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory CLK KHKL Valid address V ...
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... V OL READ burst identified (WE# = HIGH) Note: Nondefault BCR settings: latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during delay. PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory t KHKL t CLK t CEM t ABA t BOE t OLZ t KHTL t KOH ...
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... OH DQ[15: READ burst identified (WE# = HIGH) Note: Nondefault BCR settings: fixed latency; latency code 4 (5 clocks); WAIT active LOW; WAIT asserted during delay. PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory t CLK AVH AADV t CEM High-Z Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... V OL READ burst identified (WE# = HIGH) Note: Nondefault BCR settings: fixed latency; latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during delay. PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory t KHKL t CLK AADV t CEM BOE t OLZ ...
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... CLK can be stopped LOW or HIGH but must be static, with no LOW-to-HIGH transitions dur- ing burst suspend. 3. OE# can stay LOW during burst suspend. If OE# is LOW, DQ[15:0] will continue to output valid data. PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory t CLK t CEM t BOE t KOH Valid output ...
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... CLK after WAIT asserts with BCR[ before the fourth CLK after WAIT asserts with BCR[8] = 1). Micron devices are fully compatible with the CellularRAM Workgroup specification that requires CE HIGH 1 cycle sooner than shown here. PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Note KHTL Valid ...
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... Figure 39: CE#-Controlled Asynchronous WRITE A[21:0] ADV# LB#/UB# OE# WE# DQ[15:0] DQ[15:0] OUT WAIT PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Valid address CE WPH High WHZ CEW V OH High Timing Diagrams CPH Valid input t HZ High-Z Don’ ...
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... Figure 40: LB#/UB#-Controlled Asynchronous WRITE A[21:0] ADV# CE# LB#/UB# OE# WE# DQ[15:0] DQ[15:0] OUT WAIT PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Valid address WPH High WHZ CEW V OH High Timing Diagrams Valid input t HZ High-Z Don’t Care Micron Technology, Inc., reserves the right to change products or specifications without notice. © ...
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... Figure 41: WE#-Controlled Asynchronous WRITE A[21:0] ADV# CE# LB#/UB# OE# WE# DQ[15:0] DQ[15:0] OUT WAIT PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory V IH Valid address WPH High WHZ CEW V OH High Timing Diagrams Valid input High-Z Don’t Care Micron Technology, Inc., reserves the right to change products or specifications without notice. © ...
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... Figure 42: WE#-Controlled Asynchronous WRITE Using ADV# A[21:0] ADV# CE# LB#/UB# OE# WE# DQ[15:0] DQ[15:0] OUT WAIT PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory V IH Valid address AVS t AVH VPH CVS High WHZ CEW V IH High Timing Diagrams ...
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... WAIT active LOW; WAIT asserted during delay; burst length 4; burst wrap enabled. 2. WAIT asserts for LC cycles for both fixed and variable latency latency code (BCR[13:11]). required if PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory t CLK CEM t KHTL Note ...
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... WAIT active LOW; WAIT asserted during delay; burst length 4; burst wrap enabled. 2. WAIT asserts for LC cycles for both fixed and variable latency latency code (BCR[13:11]). required if PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory t CLK AVH CEM t KHTL Note ...
Page 58
... WAIT or that use WAIT to abort on an end-of-row condition. 4. Micron devices are fully compatible with the CellularRAM Workgroup specification that requires CE HIGH 1 cycle sooner than shown here. PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Note KHTL Note 3 ...
Page 59
... CE# can stay LOW between burst READ and burst WRITE operations, but CE# must not remain LOW longer than pages 60 through 62) for cases where CE# stays LOW between bursts. PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Valid address ...
Page 60
... Burst interrupt shown on first allowable clock (such as after the first data received by the controller). PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory t CLK READ burst interrupted with new READ or WRITE. See Note ...
Page 61
... Burst interrupt shown on first allowable clock (such as after first data word written). 3. CE# can stay LOW between burst operations, but CE# must not remain LOW longer than t CEM. PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory WRITE burst interrupted with new WRITE or READ. See Note 2. t CLK Valid ...
Page 62
... CE# can stay LOW between burst operations, but CE# must not remain LOW longer than t CEM. PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory WRITE burst interrupted with new WRITE or READ. See Note 2. t CLK t SP Valid ...
Page 63
... HIGH. CE# can stay LOW when transitioning to fixed-latency burst READs. A refresh opportunity must be provided every following two conditions: a) clocked CE# HIGH or b) CE# HIGH for longer than 15ns. PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory t CLK Valid address ...
Page 64
... HIGH. CE# can stay LOW when transitioning to fixed-latency burst READs. A refresh opportunity must be provided every following two conditions: a) clocked CE# HIGH or b) CE# HIGH for longer than 15ns. PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory t CLK Valid address ...
Page 65
... HIGH. CE# can stay LOW when transitioning from fixed-latency burst READs. A refresh opportunity must be provided every following two conditions: a) clocked CE# HIGH or b) CE# HIGH for longer than 15ns. PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory t CLK CBPH t HZ ...
Page 66
... HIGH. CE# can stay LOW when transitioning from fixed-latency burst READs. A refresh opportunity must be provided every following two conditions: a) clocked CE# HIGH or b) CE# HIGH for longer than 15ns. PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory t CLK t VPH CBPH ...
Page 67
... DQ[15:0] High-Z Data IN/OUT Notes: 1. When configured for synchronous mode (BCR[15] = 0), CE# must remain HIGH for at least 5ns ( after CE#-controlled WRITEs. PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Valid address CPH Note High-Z Data CPH) to schedule the appropriate refresh interval. Otherwise, Micron Technology, Inc ...
Page 68
... V DQ[15:0] IH High-Z IN/OUT V IL Notes: 1. When configured for synchronous mode (BCR[15] = 0), CE# must remain HIGH for at least 5ns ( after CE#-controlled WRITEs. PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Valid address t AVH CPH Note WPH V OH ...
Page 69
... All dimensions are in millimeters; MAX/MIN or typical (TYP) where noted. 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. 3. The MT45W4MW16BCGB uses “green” packaging. 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc ...