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MT48V8M16LFB4-8 IT:G TR
MT48V8M16LFB4-8 IT:G TR | |
|---|---|
| Manufacturer Part Number | MT48V8M16LFB4-8 IT:G TR |
| Description | IC SDRAM 128MBIT 125MHZ 54VFBGA |
| Manufacturer | Micron Technology Inc |
| MT48V8M16LFB4-8 IT:G TR datasheets |
|
Availability: By request
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Warranty: 60 days
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Specifications of MT48V8M16LFB4-8 IT:G TR | |||
|---|---|---|---|
| Format - Memory | RAM | Memory Type | Mobile SDRAM |
| Memory Size | 128M (8Mx16) | Speed | 125MHz |
| Interface | Parallel | Voltage - Supply | 2.3 V ~ 2.7 V |
| Operating Temperature | -40°C ~ 85°C | Package / Case | 54-VFBGA |
| Lead Free Status / RoHS Status | Lead free / RoHS Compliant | ||
PrevNext
5. The following states must not be interrupted by any executable command; COMMAND
INHIBIT or NOP commands must be applied on each positive clock edge during these states.
Refreshing starts with registration of an AUTO REFRESH command and ends when
met. After
6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that all banks are idle.
8. May or may not be bank-specific; if all banks are to be precharged, all must be in a valid
state for precharging.
9. Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, regard-
less of bank.
10. READs or WRITEs listed in the Command (Action) column include READs or WRITEs with
auto precharge enabled and READs or WRITEs with auto precharge disabled.
11. Does not affect the state of the bank and acts as a NOP to that bank.
PDF: 09005aef807f4885/Source: 09005aef8071a76b
128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN
t
RFC is met, the SDRAM will be in the all banks idle state.
Accessing mode
Starts with registration of a LOAD MODE REGISTER command and
t
register:
ends when
MRD has been met. After
be in the all banks idle state.
Precharging all: Starts with registration of a PRECHARGE ALL command and ends
t
when
RP is met. After
Micron Technology, Inc., reserves the right to change products or specifications without notice.
46
128Mb: x16, x32 Mobile SDRAM
t
MRD is met, the SDRAM will
t
RP is met, all banks will be in the idle state.
©2001 Micron Technology, Inc. All rights reserved.
READs
t
RFC is
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