MT47H32M8BP-5E:B TR Micron Technology Inc, MT47H32M8BP-5E:B TR Datasheet
MT47H32M8BP-5E:B TR
Specifications of MT47H32M8BP-5E:B TR
Related parts for MT47H32M8BP-5E:B TR
MT47H32M8BP-5E:B TR Summary of contents
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DDR2 SDRAM MT47H64M4 – 16 Meg banks MT47H32M8 – 8 Meg banks MT47H16M16 – 4 Meg banks Features • +1.8V ±0.1V +1.8V ±0.1V DD ...
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... Table 2: Addressing Parameter Configuration 16 Meg banks Refresh count Row address Bank address Column address Figure 1: 256Mb DDR2 Part Numbers Example Part Number: MT47H32M8BP-3 :B MT47H Configuration Configuration 64 Meg x 4 64M4 32 Meg x 8 32M8 16 Meg x 16 16M16 Package Pb-free 84-ball 8mm x 14mm FBGA ...
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Contents State Diagram .................................................................................................................................................. 8 Functional Description ..................................................................................................................................... 9 Industrial Temperature ................................................................................................................................ 9 Automotive Temperature ........................................................................................................................... 10 General Notes ............................................................................................................................................ 10 Functional Block Diagrams ............................................................................................................................. 11 Ball Assignments and Descriptions ................................................................................................................. 13 Packaging ...................................................................................................................................................... 17 Package Dimensions .................................................................................................................................. 17 FBGA ...
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Off-Chip Driver (OCD) Impedance Calibration ............................................................................................ 77 Posted CAS Additive Latency (AL) ............................................................................................................... 77 Extended Mode Register 2 (EMR2) .................................................................................................................. 79 Extended Mode Register 3 (EMR3) .................................................................................................................. 80 Initialization .................................................................................................................................................. 81 ACTIVATE ...................................................................................................................................................... 85 READ ............................................................................................................................................................. 87 READ with Precharge ...
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List of Tables Table 1: Key Timing Parameters ...................................................................................................................... 1 Table 2: Addressing ......................................................................................................................................... 2 Table 3: FBGA 60-Ball – x4, x8 and 84-Ball – x16 Descriptions .......................................................................... 15 Table 4: Input Capacitance ............................................................................................................................ 19 Table 5: Absolute Maximum DC ...
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List of Figures Figure 1: 256Mb DDR2 Part Numbers .............................................................................................................. 2 Figure 2: Simplified State Diagram ................................................................................................................... 8 Figure 3: 64 Meg x 4 Functional Block Diagram .............................................................................................. 11 Figure 4: 32 Meg x 8 Functional Block Diagram .............................................................................................. 12 ...
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Figure 51: Bank Read – Without Auto Precharge ............................................................................................. 94 Figure 52: Bank Read – with Auto Precharge ................................................................................................... 95 Figure 53: x4, x8 Data Output Timing – Figure 54: x16 Data Output Timing – Figure 55: Data Output Timing ...
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State Diagram Figure 2: Simplified State Diagram OCD default Setting (E)MRS MRS EMRS WRITE Writing WRITE A Writing with auto precharge 1. This diagram provides the basic command flow not comprehensive and does not Note: PDF: 09005aef8117c187 256MbDDR2.pdf ...
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... A bidirectional data strobe (DQS, DQS#) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR2 SDRAM during READs and by the memory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs. The x16 offering has two data strobes, one for the lower byte (LDQS, LDQS#) and one for the upper byte (UDQS, UDQS#). The DDR2 SDRAM operates from a differential clock (CK and CK#) ...
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Automotive Temperature The automotive temperature (AT) option, if offered, has two simultaneous require- ments: ambient temperature surrounding the device cannot be less than –40°C or greater than +105°C, and the case temperature cannot be less than –40°C or greater than ...
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... Functional Block Diagrams The DDR2 SDRAM is a high-speed CMOS, dynamic random access memory inter- nally configured as a multibank DRAM. Figure 3: 64 Meg x 4 Functional Block Diagram ODT Control CKE logic CK CK# CS# RAS# CAS# WE# Refresh 13 Row- Mode counter registers address MUX 15 13 ...
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... Column 0, Column 1 Column 0, Column 1 Bank 3 Bank 3 Bank 2 Bank 2 Bank 1 Bank 1 64 READ Bank 0 Bank 0 13 latch row- address 8,192 Memory latch and array decoder (8,192 x 128 x 64) Sense amplifiers 8,192 64 I/O gating DM mask logic Bank WRITE control FIFO logic 128 64 and ...
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Ball Assignments and Descriptions Figure 6: 60-Ball FBGA – x4, x8 Ball Assignments (Top View NF, DQ6 C V DDQ D NF, DQ4 E V DDL F G RFU ...
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Figure 7: 84-Ball FBGA – x16 Ball Assignments (Top View DQ14 C V DDQ D DQ12 DQ6 G V DDQ H DQ4 J V DDL K L RFU ...
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... Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command deter- mines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BA[1:0]) or all banks (A10 HIGH) ...
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Table 3: FBGA 60-Ball – x4, x8 and 84-Ball – x16 Descriptions (Continued) Symbol Type Description LDQS, LDQS# I/O Data strobe for lower byte: LDQS# is only used when differential data strobe mode is enabled via the LOAD MODE command. ...
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Packaging Package Dimensions Figure 8: 84-Ball, FBGA Package (8mm x 14mm) – x16 Seating plane C 0.12 C 84X Ø0.45 Solder ball material: Pb-free – (SAC305) SnAgCu Pb – (Eutectic) SnPbAg Dimensions apply to solder balls post-reflow. 0.80 TYP 1. ...
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Figure 9: 60-Ball, FBGA Package (8mm x 12mm) – x4, x8 Seating plane C 0.12 C 60X Ø0.45 Solder ball material: Pb-free – (SAC305) SnAgCu Pb – (Eutectic) SnPbAg Dimensions apply to solder balls post-reflow. 0.8 TYP Note: 1. All ...
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FBGA Package Capacitance Table 4: Input Capacitance Parameter Input capacitance: CK, CK# Delta input capacitance: CK, CK# Input capacitance: Address balls, bank address balls, CS#, RAS#, CAS#, WE#, CKE, ODT Delta input capacitance: Address balls, bank address balls, CS#, RAS#, ...
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Electrical Specifications – Absolute Ratings Stresses greater than those listed in Table 5 may cause permanent damage to the de- vice. This is a stress rating only, and functional operation of the device at these or any other conditions outside ...
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Table 6: Temperature Limits Parameter Storage temperature Operating temperature: commercial Operating temperature: industrial Operating temperature: automotive 1. MAX storage case temperature T Notes: 2. MAX operating case temperature T 3. Device functionality is not guaranteed if the device exceeds maximum ...
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Table 7: Thermal Impedance Die Revision Package Substrate 1 B 60-ball 2-layer 4-layer 84-ball 2-layer 4-layer Last shrink 60-ball 2-layer 2 target 4-layer 84-ball 2-layer 4-layer 1. Thermal resistance data is based on a number of samples from multiple lots ...
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Electrical Specifications – Specifications and Conditions DD Table 8: General I Parameters DD I Parameters RCD ( RRD ( x4/x8 (1KB) DD ...
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Table 10: DDR2 I Specifications and Conditions DD Notes: 1–7 apply to the entire table Parameter/Condition Operating one bank active-precharge current RAS = DD DD ...
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Table 10: DDR2 I Specifications and Conditions (Continued) DD Notes: 1–7 apply to the entire table Parameter/Condition t t Burst refresh current mand at every RFC (I ) interval; CKE is HIGH, CS ...
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AC Timing Operating Specifications Table 11: AC Operating Specifications and Conditions Not all speed grades listed may be supported for this device; refer to the title page for speeds supported; Notes: 1–5 apply to the entire table +1.8V ...
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Table 11: AC Operating Specifications and Conditions (Continued) Not all speed grades listed may be supported for this device; refer to the title page for speeds supported; Notes: 1–5 apply to the entire table +1.8V ±0.1V ...
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Table 11: AC Operating Specifications and Conditions (Continued) Not all speed grades listed may be supported for this device; refer to the title page for speeds supported; Notes: 1–5 apply to the entire table +1.8V ±0.1V ...
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Table 11: AC Operating Specifications and Conditions (Continued) Not all speed grades listed may be supported for this device; refer to the title page for speeds supported; Notes: 1–5 apply to the entire table +1.8V ±0.1V ...
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Table 11: AC Operating Specifications and Conditions (Continued) Not all speed grades listed may be supported for this device; refer to the title page for speeds supported; Notes: 1–5 apply to the entire table +1.8V ±0.1V ...
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Table 11: AC Operating Specifications and Conditions (Continued) Not all speed grades listed may be supported for this device; refer to the title page for speeds supported; Notes: 1–5 apply to the entire table +1.8V ±0.1V ...
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Table 11: AC Operating Specifications and Conditions (Continued) Not all speed grades listed may be supported for this device; refer to the title page for speeds supported; Notes: 1–5 apply to the entire table +1.8V ±0.1V ...
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Table 11: AC Operating Specifications and Conditions (Continued) Not all speed grades listed may be supported for this device; refer to the title page for speeds supported; Notes: 1–5 apply to the entire table +1.8V ±0.1V ...
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All voltages are referenced to V Notes: 2. Tests for AC timing Outputs measured with equivalent load (see Figure 14 (page 43)). 4. AC timing and I 5. The AC and DC input level specifications are as ...
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The inputs to the DRAM must be aligned to the associated clock, that is, the actual clock 19. The DRAM output timing is aligned to the nominal or average clock. Most output param- 20. When DQS is used single-ended, ...
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V 32. For each input signal—not the group collectively. 33. There are two sets of values listed for command/address: 34. This is applicable to READ cycles only. WRITE cycles generally require additional time 35. READs and WRITEs with auto ...
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ODT turn-on time 47. ODT turn-off time 48. Half-clock output parameters must be derated by the actual 49. The -187E maximum limit is 2 × 50. Should use 8 AC and DC Operating Conditions Table 12: Recommended DC Operating ...
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ODT DC Electrical Characteristics Table 13: ODT DC Electrical Characteristics All voltages are referenced Parameter effective impedance value for 75Ω setting R TT EMR (A6, A2 effective impedance value for 150Ω setting R TT ...
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Input Electrical Characteristics and Operating Conditions Table 14: Input DC Logic Levels All voltages are referenced Parameter Input high (logic 1) voltage Input low (logic 0) voltage 1. V Note: Table 15: Input AC Logic Levels All ...
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Table 16: Differential Input Logic Levels All voltages referenced Parameter DC input signal voltage DC differential input voltage AC differential input voltage AC differential cross-point voltage Input midpoint voltage 1. V Notes ...
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Numbers in diagram reflect nominal values (V PDF: 09005aef8117c187 256MbDDR2.pdf - Rev. M 7/09 EN Input Electrical Characteristics and Operating Conditions 41 Micron Technology, Inc. reserves the right to change products or specifications without notice. 256Mb: x4, x8, x16 ...
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Output Electrical Characteristics and Operating Conditions Table 17: Differential AC Output Parameters Parameter AC differential cross-point voltage AC differential voltage swing 1. The typical value of V Note: Figure 13: Differential Output Signal Levels Table 18: ...
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Table 19: Output Characteristics Parameter Output impedance Pull-up and pull-down mismatch Output slew rate 1. Absolute specifications: 0°C ≤ T Notes: 2. Impedance measurement conditions for output source DC current Mismatch is an absolute value between pull-up and ...
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Output Driver Characteristics Figure 15: Full Strength Pull-Down Characteristics 120 100 Table 20: Full Strength Pull-Down Current (mA) Voltage (V) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 ...
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Figure 16: Full Strength Pull-Up Characteristics 0 –20 –40 –60 –80 –100 –120 Table 21: Full Strength Pull-Up Current (mA) Voltage (V) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 ...
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Figure 17: Reduced Strength Pull-Down Characteristics Table 22: Reduced Strength Pull-Down Current (mA) Voltage (V) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 ...
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Figure 18: Reduced Strength Pull-Up Characteristics 0 –10 –20 –30 –40 –50 –60 –70 Table 23: Reduced Strength Pull-Up Current (mA) Voltage (V) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 ...
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Power and Ground Clamp Characteristics Power and ground clamps are provided on the following input-only balls: Address balls, bank address balls, CS#, RAS#, CAS#, WE#, ODT, and CKE. Table 24: Input Clamp Characteristics Voltage Across Clamp (V) 0.0 0.1 0.2 ...
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AC Overshoot/Undershoot Specification Some revisions will support the 0.9V maximum average amplitude instead of the 0.5V maximum average amplitude shown in Table 25 and Table 26. Table 25: Address and Control Balls Applies to address balls, bank address balls, CS#, ...
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Table 27: AC Input Test Conditions Parameter Input setup timing measurement reference level address balls, bank address balls, CS#, RAS#, CAS#, WE#, ODT, DM, UDM, LDM, and CKE Input hold timing measurement reference level address balls, bank address balls, CS#, ...
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Input Slew Rate Derating For all input signals, the total by adding the data sheet value, respectively. Example: t IS, the nominal slew rate for a rising signal, is defined as the slew rate between the last crossing of V ...
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Table 28: DDR2-400/533 Setup and Hold Time Derating Values ( Command/Address Slew Rate (V/ns) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.25 0.2 0.15 0.1 PDF: 09005aef8117c187 256MbDDR2.pdf - Rev. M 7/09 EN ...
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Table 29: DDR2-667/800/1066 Setup and Hold Time Derating Values ( Command/ Address Slew 2.0 V/ns Rate (V/ns) Δ 4.0 +150 3.5 +143 3.0 +133 2.5 +120 2.0 +100 1.5 +67 1.0 0 0.9 –5 0.8 –13 0.7 –22 ...
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Figure 22: Nominal Slew Rate for CK# V DDQ V IH(AC)min V IH(DC)min V REF(DC) V IL(DC)max V IL(AC)max Setup slew rate falling signal Figure 23: Tangent Line for CK# V DDQ V IH(AC)min V IH(DC)min V REF(DC) V IL(DC)max ...
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Figure 24: Nominal Slew Rate for CK# V DDQ V IH(AC)min V IH(DC)min V REF(DC) V IL(DC)max V IL(AC)max V Figure 25: Tangent Line for V IH(AC)min V IH(DC)min V REF(DC) V IL(DC)max V IL(AC)max Hold slew rate rising signal ...
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Table 30: DDR2-400/533 DS, All units are shown in picoseconds DQ 4.0 V/ns 3.0 V/ns Slew Δ Δ Δ Δ Rate (V/ns 2.0 125 45 125 45 1 ...
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Table 31: DDR2-667/800/1066 All units are shown in picoseconds DQ 2.8 V/ns 2.4 V/ns Slew Δ Δ Δ Δ Rate (V/ns 2.0 100 63 100 63 1 1.0 ...
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Table 32: Single-Ended DQS Slew Rate Derating Values Using Reference points indicated in bold; Derating values are to be used with base 2.0 V/ns 1.8 V/ (V/ns 2.0 130 53 130 ...
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Table 34: Single-Ended DQS Slew Rate Fully Derated (DQS Reference points indicated in bold 2.0 V/ns 1.8 V/ (V/ns 2.0 355 341 355 341 1.5 364 340 364 ...
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Figure 26: Nominal Slew Rate for DQS 1 DQS DDQ V IH(AC)min V IH(DC)min V REF(DC) V IL(DC)max V IL(AC)max V 1. DQS, DQS# signals must be monotonic between V Note: Figure 27: Tangent Line for DQS 1 ...
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Figure 28: Nominal Slew Rate for DQS 1 DQS DDQ V IH(AC)min V IH(DC)min V REF(DC) V IL(DC)max V IL(AC)max V 1. DQS, DQS# signals must be monotonic between V Note: Figure 29: Tangent Line for DQS 1 ...
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Figure 30: AC Input Test Signal Waveform Command/Address Balls Logic levels V levels REF Figure 31: AC Input Test Signal Waveform for Data with DQS, DQS# (Differential) Logic levels V levels REF PDF: 09005aef8117c187 256MbDDR2.pdf - Rev. M 7/09 EN ...
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Figure 32: AC Input Test Signal Waveform for Data with DQS (Single-Ended) Logic levels V levels REF Figure 33: AC Input Test Signal Waveform (Differential PDF: 09005aef8117c187 256MbDDR2.pdf - Rev. M 7/09 EN 256Mb: x4, x8, ...
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Commands Truth Tables The following tables provide a quick reference of available DDR2 SDRAM commands, including CKE power-down modes and bank-to-bank commands. Table 36: Truth Table – DDR2 Commands Notes: 1–3 apply to the entire table Previous Function Cycle LOAD ...
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Bank addresses (BA) determine which bank operated upon. BA during a LOAD 7. SELF REFRESH exit is asynchronous. 8. Burst reads or writes cannot be terminated or interrupted. See Figure 47 9. ...
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The following states must not be interrupted by any executable command (DESELECT or 6. All states and sequences not shown are illegal or reserved. 7. Not bank-specific; requires that all banks are idle and bursts are not in progress. ...
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Table 38: Truth Table – Current State Bank n – Command to Bank m Notes: 1–6 apply to the entire table Current State CS# RAS# Any Idle X X Row L L active, active ...
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REFRESH and LOAD MODE commands may only be issued when all banks are idle. 5. Not used. 6. All states and sequences not shown are illegal or reserved. 7. READs or WRITEs listed in the Command/Action column include READs ...
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... AL clock cycles. Input data appearing on the DQ is written to the memory array subject to the DM input logic level appearing coincident with the data given DM signal is registered LOW, the corresponding data will be written to memory; if the DM signal is registered HIGH, the corresponding data inputs will be ignored, and a WRITE will not be executed to that byte/column location (see Figure 64 (page 107)) ...
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PRECHARGE The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row activation a specified time ( concurrent auto precharge, where ...
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Burst Length Burst length is defined by bits M0–M2, as shown in Figure 34. Read and write accesses to the DDR2 SDRAM are burst-oriented, with the burst length being programmable to either four or eight. The burst length determines the ...
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Burst Type Accesses within a given burst may be programmed to be either sequential or inter- leaved. The burst type is selected via bit M3, as shown in Figure 34. The ordering of accesses within a burst is determined by ...
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Write Recovery Write recovery (WR) time is defined by bits M9–M11, as shown in Figure 34 (page 71). The WR register is used by the DDR2 SDRAM during WRITE with auto precharge opera- tion. During WRITE with auto precharge operation, ...
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CAS Latency (CL) The CAS latency (CL) is defined by bits M4–M6, as shown in Figure 34 (page 71 the delay, in clock cycles, between the registration of a READ command and the availa- bility of the first ...
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... Figure 36. The EMR is programmed via the LM command and will retain the stored information until it is programmed again or the device loses power. Reprogramming the EMR will not alter the contents of the memory array, provided it is performed correctly. ...
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DLL Enable/Disable The DLL may be enabled or disabled by programming bit E0 during the LM command, as shown in Figure 36 (page 75). These specifications are applicable when the DLL is enabled for normal operation. DLL enable is required ...
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On-Die Termination (ODT) ODT effective resistance, R Figure 36 (page 75). The ODT feature is designed to improve signal integrity of the mem- ory channel by allowing the DDR2 SDRAM controller to independently turn on/off ODT for any or all ...
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Figure 37: READ Latency T0 T1 CK# CK Command ACTIVE n READ n DQS, DQS# t RCD (MIN) DQ Notes Shown with nominal Figure 38: WRITE Latency ...
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... LM command and will retain the stored information until it is program- med again or until the device loses power. Reprogramming the EMR will not alter the contents of the memory array, provided it is performed correctly. Bit E7 (A7) must be programmed as “1” to provide a faster refresh rate on IT and AT ...
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... EMR3 is programmed via the LM command and will retain the stored information until it is programmed again or until the device loses power. Reprogramming the EMR will not alter the contents of the memory array, provided it is performed correctly. EMR3 must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time tion ...
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Initialization DDR2 SDRAM must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Figure 41 (page 82) illustrates, and the notes outline, the sequence required for power-up and initialization. ...
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Figure 41: DDR2 Power-Up and Initialization DDL V VTD 1 DDQ REF Tb0 T0 Ta0 LVCMOS SSTL_18 2 low level 2 CKE low level ...
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Applying power; if CKE is maintained below 0.2 × V Notes: 2. CKE requires LVCMOS input levels prior to state T0 to ensure DQs are High-Z during de- 3. For a minimum of 200µs after stable power and clock ...
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Issue two or more REFRESH commands. 11. Issue a LOAD MODE command to the MR with LOW initialize device operation 12. Issue a LOAD MODE command to the EMR to enable OCD default by setting bits ...
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ACTIVATE Before any READ or WRITE commands can be issued to a bank within the DDR2 SDRAM, a row in that bank must be opened (activated), even when additive latency is used. This is accomplished via the ACTIVATE command, which ...
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Figure 43: Multibank Activate Restriction T0 T1 CK# CK Command ACT READ Row Col Address Bank address Bank a Bank a t RRD (MIN) Note: 1. DDR2-533 (-37E x8), PDF: 09005aef8117c187 256MbDDR2.pdf - Rev ...
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READ READ bursts are initiated with a READ command. The starting column and bank ad- dresses are provided with the READ command, and auto precharge is either enabled or disabled for that burst access. If auto precharge is enabled, the ...
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Figure 44: READ Latency CK# Command Address DQS, DQS# CK# Command Address DQS, DQS# CK# Command Address DQS, DQS data-out from column n. Notes Three subsequent elements of data-out appear in ...
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Figure 45: Consecutive READ Bursts CK# Command Address DQS, DQS# CK# Command Address DQS, DQS ( data-out from column n (or column b). Notes Three subsequent elements of data-out appear ...
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Figure 46: Nonconsecutive READ Bursts CK# Command Address DQS, DQS# CK# Command Address DQS, DQS ( data-out from column n (or column b). Notes Three subsequent elements of data-out appear ...
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Figure 47: READ Interrupted by READ T0 T1 CK# CK READ 1 NOP 2 Command Valid 4 Address A10 DQS, DQS ( CCD required; auto precharge must be disabled ...
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Examples of READ-to-PRECHARGE for are shown in Figure 49 and in Figure 50 for The delay from READ-to-PRECHARGE period to the same bank ...
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READ with Auto Precharge If A10 is high when a READ command is issued, the READ with auto precharge function is engaged. The DDR2 SDRAM starts an auto precharge operation on the rising clock edge that (BL/2) ...
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Figure 51: Bank Read – Without Auto Precharge T0 T1 CK# CK CKE NOP 1 Command ACT RA Address A10 RA Bank address Bank x DM Case (MIN) and t DQSCK (MIN) DQS, DQS Case ...
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Figure 52: Bank Read – with Auto Precharge CKE Command 1 NOP 1 ACT Address RA A10 RA Bank address Bank x DM Case (MIN) and t DQSCK (MIN) DQS, DQS# ...
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Figure 53: x4, x8 Data Output Timing – CK# CK DQS# DQS 3 DQ (last data valid (first data no longer valid) DQ (last data valid) DQ ...
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Figure 54: x16 Data Output Timing – CK# CK LDSQ# LDQS 3 DQ (last data valid (first data no longer valid (last data valid) ...
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The data valid window is derived for each DQS transition and is 7. DQ8, DQ9, DQ10, D11, DQ12, DQ13, DQ14, or DQ15. Figure 55: Data Output Timing – CK# CK DQS#/DQS or LDQS#/LDQS/UDQ#/UDQS 3 DQ (last ...
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WRITE diagrams show the nominal case, and where the two extreme cases ( [MIN] and (page 100) shows the nominal case and the extremes of tion of a burst, assuming no other commands have been initiated, the DQ will ...
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Figure 56: Write Burst Command Address t DQSS (NOM) DQS, DQS# t DQSS (MIN) DQS, DQS# t DQSS (MAX) DQS, DQS# 1. Subsequent rising DQS signals must align to the clock within Notes data-in for column ...
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Figure 57: Consecutive WRITE-to-WRITE Command Address t DQSS (NOM) DQS, DQS# 1. Subsequent rising DQS signals must align to the clock within Notes etc. = data-in for column b, etc. 3. Three subsequent elements of data-in are ...
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Figure 59: WRITE Interrupted by WRITE T0 T1 CK# CK WRITE 1 a NOP 2 Command Valid 5 Address A10 DQS, DQS 2-clock requirement required and auto precharge must be disabled (A10 ...
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Figure 60: WRITE-to-READ T0 T1 CK# CK Command WRITE NOP Bank a, Address Col b WL ± t DQSS t DQSS (NOM) DQS, DQS DQSS (MIN DQSS DQS, DQS DQSS (MAX) ...
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Figure 61: WRITE-to-PRECHARGE T0 T1 CK# CK Command WRITE NOP Bank a, Address Col b t DQSS (NOM DQSS DQS# DQS DQSS (MIN DQSS DQS# DQS DQSS (MAX) ...
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Figure 62: Bank Write – Without Auto Precharge CKE NOP 1 Command ACT RA Address A10 RA Bank select Bank x DQS, DQS Notes: 1. NOP commands are shown for ease ...
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Figure 63: Bank Write – with Auto Precharge CKE NOP 1 Command ACT RA Address A10 RA Bank select Bank x DQS, DQS NOP commands are shown for ease of ...
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Figure 64: WRITE – DM Operation CK CKE NOP 1 NOP 1 Command ACT Address RA A10 RA Bank select Bank x DQS, DQS Notes: 1. NOP commands are shown for ...
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Figure 65: Data Input Timing CK# CK DQS DQS Notes Subsequent rising DQS signals must align to the clock within 4. WRITE command issued at T0. 5. For x16, LDQS controls the lower byte and ...
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REFRESH The commercial temperature DDR2 SDRAM requires REFRESH cycles at an average in- terval of 7.8125µs (MAX) and all rows in all banks must be refreshed at least once every 64ms. The refresh period begins when the REFRESH command is ...
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SELF REFRESH The SELF REFRESH command is initiated when CKE is LOW. The differential clock should remain stable and meet refresh mode. The procedure for exiting self refresh requires a sequence of commands. First, the differential clock must be stable ...
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Figure 67: Self Refresh CKE 1 Command NOP REF ODT 6 t AOFD/ t AOFPD 6 Address DQS#, DQS Enter self refresh mode (synchronous) 1. Clock ...
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Power-Down Mode DDR2 SDRAM supports multiple power-down modes that allow significant power sav- ings over normal operating modes. CKE is used to enter and exit different power-down modes. Power-down entry and exit timings are shown in Figure 68 (page 113). ...
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Figure 68: Power-Down Valid 1 Command NOP CKE Address Valid DQS, DQS Enter power-down mode this command is a PRECHARGE (or if the device is already in the idle ...
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Table 43: Truth Table – CKE Notes 1–4 apply to the entire table Previous Cycle Current State ( Power-down L L Self refresh L L Bank(s) active H All banks idle CKE (n) is ...
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Figure 69: READ-to-Power-Down or Self Refresh Entry T0 T1 CK# CK Command READ NOP CKE Address Valid A10 DQS, DQS the example shown, READ burst completes at T5; earliest power-down or self refresh Notes: 2. Power-down or ...
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Figure 71: WRITE-to-Power-Down or Self Refresh Entry T0 T1 CK# CK Command WRITE NOP CKE Address Valid A10 DQS, DQS Power-down or self refresh entry may occur after the WRITE burst completes. Note: Figure 72: ...
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Figure 73: REFRESH Command-to-Power-Down Entry CK# Command CKE 1. The earliest precharge power-down entry may occur is at T2, which is 1 × Note: Figure 74: ACTIVATE Command-to-Power-Down Entry CK# Command Address CKE 1. The earliest active power-down entry may ...
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Figure 75: PRECHARGE Command-to-Power-Down Entry Command Address 1. The earliest precharge power-down entry may occur is at T2, which is 1 × Note: Figure 76: LOAD MODE Command-to-Power-Down Entry CK# Command Address CKE 1. Valid address for LM command includes ...
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Precharge Power-Down Clock Frequency Change When the DDR2 SDRAM is in precharge power-down mode, ODT must be turned off and CKE must logic LOW level. A minimum of two differential clock cycles must pass after CKE goes ...
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... RESET with the exception of CKE. If CKE asynchronously drops LOW during any valid operation (including a READ or WRITE burst), the memory controller must satisfy the timing parameter turning off the clocks. Stable clocks must exist at the CK, CK# inputs of the DRAM be- fore CKE is raised HIGH, at which time the normal initialization sequence must occur (see Initialization) ...
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Figure 78: RESET Function T0 T1 CK# CK CKE ODT NOP 2 Command READ DM 3 Col n Address A10 Bank address Bank a High-Z DQS 3 High Notes: 2. Either NOP or DESELECT ...
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ODT Timing Once a 12ns delay ( bled via the EMR LOAD MODE command, ODT can be accessed under two timing categories. ODT will operate either in synchronous mode or asynchronous mode, de- pending on the state of CKE. ODT ...
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Figure 79: ODT Timing for Entering and Exiting Power-Down Mode Synchronous t First CKE latched LOW CKE Any mode except self refresh mode Applicable modes t t AOND/ AOFD Applicable timing parameters PDF: 09005aef8117c187 256MbDDR2.pdf - Rev. M 7/09 EN ...
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MRS Command to ODT Update Delay During normal operation, the value of the effective termination resistance can be changed with an EMRS set command. Figure 80: Timing for MRS Command to ODT Update Delay Command CK# ODT 2 Internal R ...
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Figure 82: ODT Timing for Slow-Exit or Precharge Power-Down Modes CK# CK Command Address CKE ODT R TT Figure 83: ODT Turn-Off Timings When Entering Power-Down Mode CK# CK Command CKE ODT R ODT R PDF: 09005aef8117c187 256MbDDR2.pdf - Rev. ...
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Figure 84: ODT Turn-On Timing When Entering Power-Down Mode CK# CK Command CKE ODT R ODT R PDF: 09005aef8117c187 256MbDDR2.pdf - Rev NOP NOP NOP TT TT Transitioning R TT 126 256Mb: x4, x8, ...
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Figure 85: ODT Turn-Off Timing When Exiting Power-Down Mode T0 T1 CK# CK Command NOP NOP CKE t CKE (MIN) ODT R TT ODT R TT PDF: 09005aef8117c187 256MbDDR2.pdf - Rev Ta0 NOP NOP ...
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Figure 86: ODT Turn-On Timing When Exiting Power-Down Mode T0 T1 CK# CK Command NOP NOP CKE t CKE (MIN) ODT R TT ODT R TT 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 www.micron.com/productsupport Customer ...