MT46H32M32LFJG-6:A TR Micron Technology Inc, MT46H32M32LFJG-6:A TR Datasheet

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MT46H32M32LFJG-6:A TR

Manufacturer Part Number
MT46H32M32LFJG-6:A TR
Description
IC DDR SDRAM 1GBIT 168VFBGA
Manufacturer
Micron Technology Inc
Datasheet

Specifications of MT46H32M32LFJG-6:A TR

Format - Memory
RAM
Memory Type
Mobile DDR SDRAM
Memory Size
1G (32M x 32)
Speed
166MHz
Interface
Parallel
Voltage - Supply
1.7 V ~ 1.95 V
Operating Temperature
0°C ~ 70°C
Package / Case
168-VFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Mobile LPDDR
168-Ball Package-on-Package (PoP) TI OMAP™
MT46HxxxMxxLxJG
Features
• Vdd/Vddq = 1.70–1.95V
• Bidirectional data strobe per byte of data (DQS)
• Internal, pipelined double data rate (DDR)
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
• 4 internal banks for concurrent operation
• Data masks (DM) for masking write data—one mask
• Programmable burst lengths (BL): 2, 4, 8, or 16
• Concurrent auto precharge option is supported
• Auto refresh and self refresh modes
• 1.8V LVCMOS-compatible inputs
• On-chip temperature sensor to control self refresh
• Partial-array self refresh (PASR)
• Deep power-down (DPD)
• STATUS READ REGISTER (SRR) supported
• Selectable output drive strength
• Clock stop capability
• 64ms refresh
Table 1:
PDF: 09005aef833508fb/Source: 09005aef83350d72
ddr_mobile_sdram_only_168b_pop.fm - Rev. B 01/09 EN
‡Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by
Architecture
Configuration
Refresh count
Row addressing
Column addressing
architecture; 2 data accesses per clock cycle
aligned with data for WRITEs
per byte
rate
Micron without notice. Products are only warranted by Micron to meet Micron’s production data sheet specifications.
Configuration Addressing
32 Meg x 16 x 4 banks
128 Meg x 16
16K (A[13:0])
1K (A[9:0])
8K
168-Ball x16, x32 Mobile LPDDR PoP (TI OMAP)Mobile DDR
2
16 Meg x 32 x 4 banks
1
64 Meg x 32
8K (A[12:0])
1K (A[9:0])
8K
1
Notes: 1. Contact factory for availability.
Options
• Vdd/Vddq
• Configuration
• Device version
• Plastic “green” package
• Timing – cycle time
• Operating temperature range
– 1.8V/1.8V
– 128 Meg x 16 (32 Meg x 16 x 4
– 64 Meg x 32 (16 Meg x 32 x 4 banks)
– 64 Meg x 16 (16 Meg x 16 x 4 banks)
– 32 Meg x 32 (8 Meg x 32 x 4 banks)
– Single die, standard addressing
– 2-die stack, standard addressing
– 168-ball VFBGA (12mm x 12mm)
– 5ns @ CL = 3
– 5.4ns @ CL = 3
– 6ns @ CL = 3
– Commercial (0° to +70°C)
– Industrial (–40°C to +85°C)
banks)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2. Contact factory for remapped SRR output.
16 Meg x 16 x 4 banks
64 Meg x 16
16K (A[13:0])
1K (A[9:0])
8K
©2008 Micron Technology, Inc. All rights reserved.
SDRAM Addendum
8 Meg x 32 x 4 banks
32 Meg x 32
8K (A[12:0])
1K (A[9:0])
Marking
8K
Preliminary
128M16
64M32
64M16
32M32
None
-54
LF
L2
JG
IT
-5
-6
H

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MT46H32M32LFJG-6:A TR Summary of contents

Page 1

Mobile LPDDR 168-Ball Package-on-Package (PoP) TI OMAP™ MT46HxxxMxxLxJG Features • Vdd/Vddq = 1.70–1.95V • Bidirectional data strobe per byte of data (DQS) • Internal, pipelined double data rate (DDR) architecture; 2 data accesses per clock cycle • Differential clock inputs ...

Page 2

... Meg x 32 Device Version LF = Single die, standard addressing L2 = Dual die, standard addressing Table 2: 168-Ball Production Part Numbers Part Numbers MT46H32M32LFJG-5:A MT46H32M32LFJG-5 IT:A MT46H32M32LFJG-54:A MT46H32M32LFJG-54 IT:A MT46H32M32LFJG-6:A MT46H32M32LFJG-6 IT:A MT46H64M32L2JG-5:A MT46H64M32L2JG-5 IT:A MT46H64M32L2JG-54:A MT46H64M32L2JG-54 IT:A MT46H64M32L2JG-6:A MT46H64M32L2JG-6 IT:A Device Marking Due to the size of the package, the Micron-standard part number is not printed on the top of the device ...

Page 3

... General Description The 1Gb Mobile LPDDR die contained within this package is a high-speed CMOS, dynamic random access memory containing 1,073,741,824 bits internally config- ured as a quad-bank DRAM. Each of the x16’s 268,435,456-bit banks is organized as 16,384 rows by 1024 columns by 16 bits. Each of the x32’s 268,435,456-bit banks is orga- nized as 8192 rows by 1024 columns by 32 bits ...

Page 4

... Address BA0, BA1 register PDF: 09005aef833508fb/Source: 09005aef83350d72 ddr_mobile_sdram_only_168b_pop.fm - Rev. B 01/09 EN 168-Ball x16, x32 Mobile LPDDR PoP (TI OMAP)Mobile DDR Bank 3 Bank 2 Bank 1 Bank 0 row- Bank 0 address memory latch array and decoder Sense amplifiers I/O gating 2 DM mask logic Bank control logic 2 Column ...

Page 5

Ball Assignments and Descriptions Figure 4: 168-Ball VFBGA (x32) Ball Assignments Notes: 1. Although not bonded to the die, these pins may be connected on the package substrate. PDF: 09005aef833508fb/Source: 09005aef83350d72 ddr_mobile_sdram_only_168b_pop.fm - Rev. B 01/09 EN 168-Ball x16, x32 ...

Page 6

Figure 5: 168-Ball VFBGA (x16) Ball Assignments DQ12 DNU DNU DQ14 Vddq UDM Vddq B DNU DNU DQ15 Vssq DQ13 UDQS Vssq C DNU DNU D DNU DNU E Vddq Vssq F DNU ...

Page 7

Table 3: x16/x32 LPDDR Ball Descriptions x16 Balls x32 Balls W23, W22, V23, V22, W22, V23, V22, U23, U23, U22, T23, T22, R23, U22, T23, T22, R23, R22, R22, P23, P22, N23, N22 P23, P22, N23, N22 AB21, AC21 AB21, ...

Page 8

Table 4: Non-Device-Specific Ball Descriptions Shared Balls x16 B12, H22, K2, K22, L2, B12, H22, K2, K22, L2, P2, AA2, AA22, AB5, P2, AA2, AA22, AB5, AB8, AB13, AB14, AB20 AB8, AB13, AB14, AB20 Miscellaneous Balls x16 A20, A21, B20, ...

Page 9

Electrical Specifications Table 5: Absolute Maximum Ratings Parameters/Conditions Vdd, Vddq relative to Vss Voltage on any pin relative to Vss Storage temperature range Stresses greater than those listed under “Absolute Maximum Ratings” may cause perma- nent damage to the device. ...

Page 10

Device Diagram Figure 6: 168-Ball VFBGA Functional Block Diagram CK# CKE RAS# CAS# WE# Address, BA0, BA1 PDF: 09005aef833508fb/Source: 09005aef83350d72 ddr_mobile_sdram_only_168b_pop.fm - Rev. B 01/09 EN 168-Ball x16, x32 Mobile LPDDR PoP (TI OMAP)Mobile DDR CS# CK LPDDR Micron Technology, ...

Page 11

Package Dimensions Figure 7: 168-Ball VFBGA Seating plane A 0.08 A 168X Ø0.326 Dimensions apply to solder balls post- reflow. Pre-reflow ball is Ø0.3 on Ø0. ...

Page 12

Revision History Rev. B, Preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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