IS61LPS51236A-250B3LI-TR ISSI, Integrated Silicon Solution Inc, IS61LPS51236A-250B3LI-TR Datasheet

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IS61LPS51236A-250B3LI-TR

Manufacturer Part Number
IS61LPS51236A-250B3LI-TR
Description
IC SRAM 18MBIT 250MHZ 165FBGA
Manufacturer
ISSI, Integrated Silicon Solution Inc
Datasheet

Specifications of IS61LPS51236A-250B3LI-TR

Format - Memory
RAM
Memory Type
SRAM - Synchronous
Memory Size
18M (512K x 36)
Speed
250MHz
Interface
Parallel
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Package / Case
165-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IS61LPS51236A-250B3LI-TR
Manufacturer:
ISSI, Integrated Silicon Solution Inc
Quantity:
10 000
256K x 72, 512K x 36, 1024K x 18
18Mb SYNCHRONOUS PIPELINED,
SINGLE CYCLE DESELECT STATIC RAM
FEATURES
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
• Burst sequence control using MODE input
• Three chip enable option for simple depth
• Common data inputs and data outputs
• Auto Power-down during deselect
• Single cycle deselect
• Snooze MODE for reduced-power standby
• JTAG Boundary Scan for PBGA package
• Power Supply
• JEDEC 100-Pin TQFP, 119-ball PBGA, 165-ball
• Lead-free available
FAST ACCESS TIME
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. N
02/12/2010
Copyright © 2010 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
IS61VPS25672A IS61LPS25672A
IS61VPS51236A IS61LPS51236A
IS61VPS102418A IS61LPS102418A
control
expansion and address pipelining
LPS: V
VPS: V
PBGA, and 209-ball (x72) packages
Symbol
t
t
KQ
KC
DD
DD
3.3V + 5%, V
2.5V + 5%, V
Parameter
Clock Access Time
Cycle Time
Frequency
DDQ
DDQ
3.3V/2.5V + 5%
2.5V + 5%
DESCRIPTION
The
and IS61LPS/VPS25672A are high-speed, low-power syn-
chronous static RAMs designed to provide burstable, high-
performance memory for communication and networking
applications. The IS61LPS/VPS51236A is organized as
524,288 words by 36 bits, the IS61LPS/VPS102418A is
organized as 1,048,576 words by 18 bits, and the IS61LPS/
VPS25672A is organized as 262,144 words by 72 bits.
Fabricated with
device integrates a 2-bit burst counter, high-speed SRAM
core, and high-drive capability outputs into a single mono-
lithic circuit. All synchronous inputs pass through regis-
ters controlled by a positive-edge-triggered single clock
input.
Write cycles are internally self-timed and are initiated by
the rising edge of the clock input. Write cycles can be one
to four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
The byte write operation is performed by using the byte
write enable (BWE) input combined with one or more
individual byte write signals (BWx). In addition, Global
Write (GW) is available for writing all bytes at one time,
regardless of the byte write controls.
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller)
input pins. Subsequent burst addresses can be generated
internally and controlled by the ADV (burst address
advance) input pin.
The mode pin is used to select the burst sequence order,
Linear burst is achieved when this pin is tied LOW.
Interleave burst is achieved when this pin is tied HIGH or
left floating.
250
250
2.6
4
ISSI
IS61LPS/VPS51236A, IS61LPS/VPS102418A,
ISSI
's advanced CMOS technology, the
200
200
3.1
5
MAY 2010
Units
MHz
ns
ns
1

Related parts for IS61LPS51236A-250B3LI-TR

IS61LPS51236A-250B3LI-TR Summary of contents

Page 1

... IS61VPS25672A IS61LPS25672A IS61VPS51236A IS61LPS51236A IS61VPS102418A IS61LPS102418A 256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • ...

Page 2

... IS61VPS25672A, IS61LPS25672A IS61VPS51236A, IS61LPS51236A, IS61VPS102418A, IS61LPS102418A BLOCK DIAGRAM CLK ADV ADSC ADSP 19/ BWE BW(a-h) x18: a,b x36: a-d x72: a-h CE CE2 CE2 POWER ZZ DOWN OE 2 MODE A0 CLK BINARY COUNTER A1 CLR MEMORY ARRAY 17/18 19/ ADDRESS REGISTER CE CLK 36 DQ(a-h) BYTE WRITE REGISTERS CLK ...

Page 3

... IS61VPS25672A, IS61LPS25672A IS61VPS51236A, IS61LPS51236A, IS61VPS102418A, IS61LPS102418A 165-PIN BGA 165-Ball, 13x15 mm BGA 1mm Ball Pitch, 11x15 Ball Array BOTTOM VIEW 209-BALL BGA 209-Ball BGA 1 mm Ball Pitch Ball Array BOTTOM VIEW Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. N 02/12/2010 119-PIN BGA 119-Ball, 14x22 mm BGA ...

Page 4

... IS61VPS25672A, IS61LPS25672A IS61VPS51236A, IS61LPS51236A, IS61VPS102418A, IS61LPS102418A PIN CONFIGURATION — 256K X 72, 209-Ball PBGA (TOP VIEW DQg DQg A BWc B DQg DQg BWh C DQg DQg D DQg DQg VSS E DQPg DQPc V DDQ F DQc DQc VSS G DQc DQc V DDQ H DQc DQc VSS J DQc DQc V DDQ ...

Page 5

... IS61VPS25672A, IS61LPS25672A IS61VPS51236A, IS61LPS51236A, IS61VPS102418A, IS61LPS102418A 119 BGA PACKAGE PIN CONFIGURATION DDQ DQc DQPc Vss E DQc DQc Vss F V DQc Vss DDQ BWc G DQc DQc H DQc DQc Vss DDQ DD K DQd DQd Vss BWd L DQd DQd M V DQd Vss DDQ N DQd ...

Page 6

... IS61VPS25672A, IS61LPS25672A IS61VPS51236A, IS61LPS51236A, IS61VPS102418A, IS61LPS102418A 119 BGA PACKAGE PIN CONFIGURATION 1M 18 (TOP VIEW DDQ DQb NC Vss E NC DQb Vss Vss DDQ BWb G NC DQb H DQb NC Vss DDQ DQb Vss L DQb NC Vss M V DQb Vss DDQ N DQb NC Vss P NC DQPb Vss ...

Page 7

... IS61VPS25672A, IS61LPS25672A IS61VPS51236A, IS61LPS51236A, IS61VPS102418A, IS61LPS102418A 165 PBGA PACKAGE PIN CONFIGURATION 512K 36 (TOP VIEW CE2 C DQPc NC V DDQ D DQc DQc V DDQ E DQc DQc V DDQ F DQc DQc V DDQ G DQc DQc V DDQ H NC Vss NC J DQd DQd V DDQ K DQd DQd V DDQ L DQd DQd ...

Page 8

... IS61VPS25672A, IS61LPS25672A IS61VPS51236A, IS61LPS51236A, IS61VPS102418A, IS61LPS102418A 165 PBGA PACKAGE PIN CONFIGURATION 1M 18 (TOP VIEW CE2 DDQ D NC DQb V DDQ E NC DQb V DDQ F NC DQb V DDQ G NC DQb V DDQ H NC Vss NC J DQb NC V DDQ K DQb NC V DDQ L DQb NC V DDQ M DQb ...

Page 9

... IS61VPS25672A, IS61LPS25672A IS61VPS51236A, IS61LPS51236A, IS61VPS102418A, IS61LPS102418A PIN CONFIGURATION 100-PIN TQFP 100 DQPc 1 DQc 2 3 DQc 4 VDDQ VSS 5 6 DQc 7 DQc DQc 8 9 DQc 10 VSS VDDQ 11 12 DQc 13 DQc 14 NC VDD VSS DQd 18 19 DQd 20 VDDQ VSS 21 22 DQd 23 DQd DQd 24 DQd ...

Page 10

... IS61VPS25672A, IS61LPS25672A IS61VPS51236A, IS61LPS51236A, IS61VPS102418A, IS61LPS102418A PIN CONFIGURATION 100-PIN TQFP 100 VDDQ 4 5 VSS DQb 8 DQb 9 10 VSS 11 VDDQ 12 DQb DQb VDD VSS 18 DQb DQb 19 20 VDDQ 21 VSS 22 DQb 23 DQb DQPb VSS 27 VDDQ 1024K x 18 PIN DESCRIPTIONS A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus ...

Page 11

... IS61VPS25672A, IS61LPS25672A IS61VPS51236A, IS61LPS51236A, IS61VPS102418A, IS61LPS102418A TRUTH TABLE (1-8) (3CE option) OPERATION ADDRESS Deselect Cycle, Power-Down None Deselect Cycle, Power-Down None Deselect Cycle, Power-Down None Deselect Cycle, Power-Down None Deselect Cycle, Power-Down None Snooze Mode, Power-Down None Read Cycle, Begin Burst ...

Page 12

... IS61VPS25672A, IS61LPS25672A IS61VPS51236A, IS61LPS51236A, IS61VPS102418A, IS61LPS102418A TRUTH TABLE (1-8) (1CE option) NEXT CYCLE Deselected Read, Begin Burst Read, Begin Burst Write, Begin Burst Read, Begin Burst Read, Begin Burst Read, Continue Burst Read, Continue Burst Read, Continue Burst Read, Continue Burst ...

Page 13

... IS61VPS25672A, IS61LPS25672A IS61VPS51236A, IS61LPS51236A, IS61VPS102418A, IS61LPS102418A INTERLEAVED BURST ADDRESS TABLE (MODE = V External Address 1st Burst Address LINEAR BURST ADDRESS TABLE (MODE = VSS) A1', A0' = 1,1 ABSOLUTE MAXIMUM RATINGS Symbol Parameter T Storage Temperature STG P Power Dissipation D I Output Current (per I/O) OUT Voltage Relative to Vss for I/O Pins ...

Page 14

... IS61VPS25672A, IS61LPS25672A IS61VPS51236A, IS61LPS51236A, IS61VPS102418A, IS61LPS102418A OPERATING RANGE (IS61LPSXXXXX) Range Ambient Temperature Commercial 0°C to +70°C Industrial –40°C to +85°C OPERATING RANGE (IS61VPSXXXXX) Range Ambient Temperature Commercial 0°C to +70°C Industrial –40°C to +85°C DC ELECTRICAL CHARACTERISTICS Symbol Parameter V Output HIGH Voltage ...

Page 15

... IS61VPS25672A, IS61LPS25672A IS61VPS51236A, IS61LPS51236A, IS61VPS102418A, IS61LPS102418A CAPACITANCE (1,2) Symbol Parameter C Input Capacitance IN C Input/Output Capacitance OUT Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions 25° MHz 3.3V I/O AC TEST CONDITIONS Parameter Input Pulse Level ...

Page 16

... IS61VPS25672A, IS61LPS25672A IS61VPS51236A, IS61LPS51236A, IS61VPS102418A, IS61LPS102418A 2.5V I/O AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load 2.5 I/O OUTPUT LOAD EQUIVALENT Z = 50Ω O Output Figure 3 16 Unit 0V to 2.5V 1 ...

Page 17

... IS61VPS25672A, IS61LPS25672A IS61VPS51236A, IS61LPS51236A, IS61VPS102418A, IS61LPS102418A READ/WRITE CYCLE SWITCHING CHARACTERISTICS Symbol Parameter f Clock Frequency MAX t Cycle Time KC t Clock High Time KH t Clock Low Time KL t Clock Access Time KQ t (2) Clock High to Output Invalid KQX (2,3) t Clock High to Output Low-Z KQLZ ...

Page 18

... IS61VPS25672A, IS61LPS25672A IS61VPS51236A, IS61LPS51236A, IS61VPS102418A, IS61LPS102418A READ/WRITE CYCLE TIMING t KC CLK ADSP t SS ADSC ADV Address RD1 BWE BWx t t CES CEH CES CEH CE2 t t CES CEH CE2 t OEQ OE t OELZ High-Z DATA OUT t KQLZ t KQ High-Z DATA IN Single Read ...

Page 19

... IS61VPS25672A, IS61LPS25672A IS61VPS51236A, IS61LPS51236A, IS61VPS102418A, IS61LPS102418A WRITE CYCLE TIMING t KC CLK ADSP ADSC ADV must be inactive for ADSP Write ADV Address WR1 BWE BWx WR1 t t CES CEH CES CEH CE2 t t CES CEH CE2 OE High-Z DATA OUT t DS High-Z DATA ...

Page 20

... IS61VPS25672A, IS61LPS25672A IS61VPS51236A, IS61LPS51236A, IS61VPS102418A, IS61LPS102418A SNOOZE MODE ELECTRICAL CHARACTERISTICS Symbol Parameter I Current during SNOOZE MODE active to input ignored PDS t ZZ inactive to input sampled PUS t ZZ active to SNOOZE current ZZI t ZZ inactive to exit SNOOZE current RZZI SNOOZE MODE TIMING CLK t PDS ...

Page 21

... IS61VPS25672A, IS61LPS25672A IS61VPS51236A, IS61LPS51236A, IS61VPS102418A, IS61LPS102418A IEEE 1149.1 SERIAL BOUNDARY SCAN (JTAG) The IS61LPS/VPSxxxxxx products have a serial boundary scan Test Access Port (TAP) in the PBGA package only. (The TQFP package not available.) This port operates in accordance with IEEE Standard 1149.1-1900, but does not include all functions required for full 1149 ...

Page 22

... IS61VPS25672A, IS61LPS25672A IS61VPS51236A, IS61LPS51236A, IS61VPS102418A, IS61LPS102418A TEST DATA OUT (TDO) The TDO output pin is used to serially clock data-out from the registers. The output is active depending on the current state of the TAP state machine (see TAP Controller State Diagram). The output changes on the falling edge of TCK and TDO is connected to the Least Significant Bit (LSB) of any register ...

Page 23

... IS61VPS25672A, IS61LPS25672A IS61VPS51236A, IS61LPS51236A, IS61VPS102418A, IS61LPS102418A TAP INSTRUCTION SET Eight instructions are possible with the three-bit instruction register and all combinations are listed in the Instruction Code table. Three instructions are listed as RESERVED and should not be used and the other five instructions are described below ...

Page 24

... IS61VPS25672A, IS61LPS25672A IS61VPS51236A, IS61LPS51236A, IS61VPS102418A, IS61LPS102418A INSTRUCTION CODES Code Instruction Description 000 EXTEST Captures the Input/Output ring contents. Places the boundary scan register between the TDI and TDO. Forces all SRAM outputs to High-Z state. This instruction is not 1149.1 compliant. 001 IDCODE Loads the ID register with the vendor ID code and places the register between TDI and TDO ...

Page 25

... IS61VPS25672A, IS61LPS25672A IS61VPS51236A, IS61LPS51236A, IS61VPS102418A, IS61LPS102418A TAP Electrical Characteristics Over the Operating Range Symbol Parameter V Output HIGH Voltage OH1 V Output HIGH Voltage OH2 V Output LOW Voltage OL1 V Output LOW Voltage OL2 V Input HIGH Voltage IH V Input LOW Voltage IL I Input Leakage Current ...

Page 26

... IS61VPS25672A, IS61LPS25672A IS61VPS51236A, IS61LPS51236A, IS61VPS102418A, IS61LPS102418A TAP AC TEST CONDITIONS (2.5V/3.3V) Input pulse levels 0 to 2.5V/0 to 3.0V Input rise and fall times Input timing reference levels Output reference levels Test load termination supply voltage Vtrig TAP TIMING 1 t THTH TCK t MVTH TMS ...

Page 27

... IS61VPS25672A, IS61LPS25672A IS61VPS51236A, IS61LPS51236A, IS61VPS102418A, IS61LPS102418A 209 BOUNDARY SCAN ORDER (256K X 72) Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. N 02/12/2010 27 ...

Page 28

... IS61VPS25672A, IS61LPS25672A IS61VPS51236A, IS61LPS51236A, IS61VPS102418A, IS61LPS102418A 165 PBGA BOUNDARY SCAN ORDER (x 36) Signal Bump Bit # Name ID Bit # 1 MODE 11P 10P 10R 11R 11H 31 12 DQa 11N 32 13 DQa 11M 33 14 DQa 11L 34 15 DQa 11K 35 16 DQa 11J 36 17 DQa 10M ...

Page 29

... IS61VPS25672A, IS61LPS25672A IS61VPS51236A, IS61LPS51236A, IS61VPS102418A, IS61LPS102418A 165 PBGA BOUNDARY SCAN ORDER (x 18) Signal Bump Bit # Name ID Bit # 1 MODE 11P 10P 10R 11R 11H 11N 11M 11L 11K 11J 36 17 DQa 10M 37 18 DQa 10L 38 19 DQa 10K 39 20 DQa 10J 40 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev ...

Page 30

... IS61VPS25672A, IS61LPS25672A IS61VPS51236A, IS61LPS51236A, IS61VPS102418A, IS61LPS102418A ORDERING INFORMATION (3.3V core/2.5V-3.3V I/O) Commercial Range: 0°C to +70°C Configuration Frequency 512Kx36 250 200 1Mx18 250 200 256Kx72 250 Industrial Range: -40°C to +85°C Configuration Frequency 512Kx36 250 200 1Mx18 250 200 256Kx72 250 ...

Page 31

... IS61VPS25672A, IS61LPS25672A IS61VPS51236A, IS61LPS51236A, IS61VPS102418A, IS61LPS102418A ORDERING INFORMATION (2.5V core/2.5V I/O) Commercial Range: 0°C to +70°C Configuration Frequency 512Kx36 250 200 1Mx18 250 200 256Kx72 250 Industrial Range: -40°C to +85°C Configuration Frequency 512Kx36 250 200 1Mx18 250 200 256Kx72 250 Integrated Silicon Solution, Inc. — ...

Page 32

... IS61VPS25672A, IS61LPS25672A IS61VPS51236A, IS61LPS51236A, IS61VPS102418A, IS61LPS102418A 32 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. N 02/12/2010 ...

Page 33

... IS61VPS25672A, IS61LPS25672A IS61VPS51236A, IS61LPS51236A, IS61VPS102418A, IS61LPS102418A Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. N 02/12/2010 33 ...

Page 34

... IS61VPS25672A, IS61LPS25672A IS61VPS51236A, IS61LPS51236A, IS61VPS102418A, IS61LPS102418A 34 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. N 02/12/2010 ...

Page 35

... IS61VPS25672A, IS61LPS25672A IS61VPS51236A, IS61LPS51236A, IS61VPS102418A, IS61LPS102418A Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. N 02/12/2010 35 ...

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