M25P80-VMW6G NUMONYX, M25P80-VMW6G Datasheet

no-image

M25P80-VMW6G

Manufacturer Part Number
M25P80-VMW6G
Description
IC FLASH 8MBIT 75MHZ 8SOIC
Manufacturer
NUMONYX
Series
Forté™r
Datasheets

Specifications of M25P80-VMW6G

Format - Memory
FLASH
Memory Type
FLASH
Memory Size
8M (1M x 8)
Speed
75MHz
Interface
SPI, 3-Wire Serial
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
Ic Interface Type
Serial, SPI
Clock Frequency
75MHz
Supply Voltage Range
2.7V To 3.6V
Memory Case Style
SOIC
No. Of Pins
8
Cell Type
NOR
Density
8Mb
Access Time (max)
8ns
Interface Type
Serial (SPI)
Boot Type
Not Required
Address Bus
1b
Operating Supply Voltage (typ)
3.3V
Operating Temp Range
-40C to 85C
Package Type
SOIC W
Sync/async
Synchronous
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (max)
3.6V
Word Size
8b
Number Of Words
1M
Supply Current
15mA
Mounting
Surface Mount
Pin Count
8
Memory Configuration
1M X 8
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M25P80-VMW6G
Manufacturer:
CET
Quantity:
1 200
Part Number:
M25P80-VMW6G
Manufacturer:
ST
0
Part Number:
M25P80-VMW6G
Manufacturer:
ST
Quantity:
20 000
Part Number:
M25P80-VMW6G
Manufacturer:
MICRON
Quantity:
3 524
Part Number:
M25P80-VMW6G
0
Part Number:
M25P80-VMW6G SO8
Manufacturer:
ST
0
Features
April 2010
SPI bus compatible serial interface
75 MHz Clock rate (maximum)
2.7 V to 3.6 V single supply voltage
8 Mbit of Flash memory
Page Program (up to 256 bytes) in 0.64 ms
(typical)
Sector Erase (512 Kbit) in 0.6 s (typical)
Bulk Erase (8 Mbit) in 8 s (typical)
Hardware Write protection: protected area size
defined by three non-volatile bits (BP0, BP1
and BP2)
Deep Power-down mode 1 µA (typical)
Electronic signatures
– JEDEC Standard two-byte signature
– Unique ID code (UID) +16 bytes of CFI
– RES instruction one-byte signature (13h)
More than 100 000 Program/Erase cycles per
sector
More than 20 years’ data retention
Packages
– RoHS compliant
Automotive Certified Parts Available
(2014h)
data
for backward compatibility
Numonyx
®
8 Mbit, low voltage, serial Flash memory
Forté™ Serial Flash Memory
Rev 23
208 mils width
SO8W (MW)
300 mils width
with 75 MHz SPI bus interface
 
PDIP8 (BA)
6 x 5 mm (MLP8)
VFDFPN8 (MP)
(MLP8 4 x 3 mm)
UFDFPN8 (MC)
M25P80
150 mils width
SO8 (MN)
www.numonyx.com
1/57
1

Related parts for M25P80-VMW6G

M25P80-VMW6G Summary of contents

Page 1

... April 2010 ® Forté™ Serial Flash Memory 8 Mbit, low voltage, serial Flash memory with 75 MHz SPI bus interface SO8W (MW) 208 mils width (MLP8)   PDIP8 (BA) 300 mils width Rev 23 M25P80 SO8 (MN) 150 mils width VFDFPN8 (MP) UFDFPN8 (MC) (MLP8 mm) 1/57 www.numonyx.com 1 ...

Page 2

... Polling During a Write, Program or Erase Cycle . . . . . . . . . . . . . . . . . . . 12 4.4 Active Power, Standby Power and Deep Power-down modes . . . . . . . . . 12 4.5 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.6 Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.7 Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.1 Write Enable (WREN 6.2 Write Disable (WRDI 6.3 Read Identification (RDID 6.4 Read Status Register (RDSR) ...

Page 3

SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 4

... List of tables Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 2. Protected area sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 3. Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 4. Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 5. Read Identification (RDID) data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 6. Status Register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 7. Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 8. Power-up timing and VWI threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 9. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 10. Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 11 ...

Page 5

... List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. VFQFPN, SO8, and PDIP8 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. Bus Master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 4. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 5. Hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 6. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 7. Write Enable (WREN) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 8. Write Disable (WRDI) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 9 ...

Page 6

... Description The M25P80 Mbit (1 Mbit × 8) Serial Flash memory, with advanced write protection mechanisms, accessed by a high speed SPI-compatible bus. The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction. The memory is organized as 16 sectors, each containing 256 pages. Each page is 256 bytes wide ...

Page 7

... VFQFPN, SO8, and PDIP8 connections 1. There is an exposed central pad on the underside of the VFQFPN package. This is pulled, internally and must not be allowed to be connected to any other voltage or signal line on the PCB See Package mechanical section for package dimensions, and how to identify pin-1. M25P80 ...

Page 8

... To start the Hold condition, the device must be selected, with Chip Select (S) driven Low. 2.6 Write Protect (W) The main purpose of this input signal is to freeze the size of the area of memory that is protected against program or erase instructions (as specified by the values in the BP2, BP1 and BP0 bits of the Status Register). ...

Page 9

V supply voltage the supply voltage. CC 2.8 V ground the reference for the V SS supply voltage. CC 9/57 ...

Page 10

... Serial Data Output (Q) line at a time, the other devices are high impedance. Resistors R (represented in that the M25P80 is not selected if the Bus Master leaves the S line in the high impedance state. As the Bus Master may enter a state where all inputs/outputs are in high impedance at ...

Page 11

Example pF, that is R*C p never leaves the SPI bus in the high impedance state for a time period shorter than 5 µs. Figure 4. SPI modes supported CPOL CPHA ...

Page 12

... Sector Erase and Bulk Erase The Page Program (PP) instruction allows bits to be reset from Before this can be applied, the bytes of memory need to have been erased to all 1s (FFh). This can be achieved either a sector at a time, using the Sector Erase (SE) instruction, or throughout the entire memory, using the Bulk Erase (BE) instruction ...

Page 13

... The environments where non-volatile memory devices are used can be very noisy. No SPI device can operate correctly in the presence of excessive noise. To help combat this, the M25P80 boasts the following data protection mechanisms: Power-On Reset and an internal timer (t inadvertent changes while the power supply is outside the operating specification. ...

Page 14

... To restart communication with the device necessary to drive Hold (HOLD) High, and then to drive Chip Select (S) Low. This prevents the device from going back to the Hold condition. 14/57 Memory content Protected area Upper half (eight sectors 15) All sectors (sixteen sectors 15) ...

Page 15

Figure 5. Hold condition activation C HOLD (standard use) Hold Condition (non-standard use) Hold Condition AI02029D 15/57 ...

Page 16

... Memory organization The memory is organized as: 1,048,576 bytes (8 bits each) 16 sectors (512 Kbits or 65,536 bytes each) 4096 pages (256 bytes each). Each page can be individually programmed (bits are programmed from 1 to 0). The device is Sector or Bulk Erasable (bits are erased from but not Page Erasable. ...

Page 17

... Figure 6. Block diagram HOLD W Control Logic Address Register and Counter High Voltage Generator I/O Shift Register 256 Byte Data Buffer FFFFFh 00000h 000FFh 256 Bytes (Page Size) X Decoder Status Register Size of the read-only memory area AI04987 17/57 ...

Page 18

... Chip Select (S) being driven Low is an exact multiple of eight. All attempts to access the memory array during a Write Status Register cycle, Program cycle or Erase cycle are ignored, and the internal Write Status Register cycle, Program cycle or Erase cycle continues unaffected. ...

Page 19

Table 4. Instruction set Instruction Release from Deep Power- down, and Read Electronic Signature RES Release from Deep Power- down 1. The RDID instruction is available only for parts made with 110 nm Technology identified with Process letter '4'. (Details ...

Page 20

Figure 8. Write Disable (WRDI) instruction sequence 20/ Instruction D High Impedance AI03750D ...

Page 21

... Device identification (two bytes) A Unique ID code (UID) followed by 16 bytes of CFI data The manufacturer identification is assigned by JEDEC, and has the value 20h for Numonyx. The device identification is assigned by the device manufacturer, and indicates the memory type in the first byte (20h), and the memory capacity of the device in the second byte (14h). ...

Page 22

Figure 9. Read Identification (RDID) instruction sequence and data-out sequence 22/57 ...

Page 23

... The status and control bits of the Status Register are as follows: 6.4.1 WIP bit The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status Register, Program or Erase cycle. When set to 1, such a cycle is in progress, when reset such cycle is in progress. ...

Page 24

Figure 10. Read Status Register (RDSR) instruction sequence and data-out sequence High Impedance Q 24/ Instruction Status Register Out 7 6 ...

Page 25

Write Status Register (WRSR) The Write Status Register (WRSR) instruction allows new values to be written to the Status Register. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable ...

Page 26

... Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction. (Attempts to write to the Status Register are rejected, and are not accepted for execution consequence, all the data bytes in the memory area that are software protected (SPM) by the Block Protect (BP2, BP1, BP0) bits of the Status Register, are also hardware protected against data modification ...

Page 27

... The instruction sequence is shown in The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes (READ) instruction. When the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely ...

Page 28

... The instruction sequence is shown in The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes at Higher Speed (FAST_READ) instruction. When the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely ...

Page 29

... Page Program (PP) The Page Program (PP) instruction allows bytes to be programmed in the memory (changing bits from 1 to 0). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). ...

Page 30

Figure 14. Page Program (PP) instruction sequence Data Byte MSB 1. Address bits A23 to A20 are Don’t Care. 30/ ...

Page 31

Sector Erase (SE) The Sector Erase (SE) instruction sets to 1 (FFh) all bits inside the chosen sector. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction ...

Page 32

Bulk Erase (BE) The Bulk Erase (BE) instruction sets all bits to 1 (FFh). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the ...

Page 33

Deep Power-down (DP) Executing the Deep Power-down (DP) instruction is the only way to put the device in the lowest consumption mode (the Deep Power-down mode). It can also be used as an extra software protection mechanism, while the ...

Page 34

... Executing this instruction takes the device out of the Deep Power-down mode. The instruction can also be used to read, on Serial Data Output (Q), the 8-bit Electronic Signature, whose value for the M25P80 is 13h. Please note that this is not the same as, or even a subset of, the JEDEC 16-bit Electronic Signature that is read by the Read Identifier (RDID) instruction ...

Page 35

... Figure 18. Release from Deep Power-down and Read Electronic Signature (RES) instruction sequence and data-out sequence Instruction D High Impedance Q 1. The value of the 8-bit Electronic Signature for the M25P80 is 13h. Figure 19. Release from Deep Power-down (RES) instruction sequence Instruction D High Impedance Dummy Bytes ...

Page 36

Power-up and Power-down At Power-up and Power-down, the device must not be selected (that is Chip Select (S) must follow the voltage applied (min) at Power-up, and then for a further delay ...

Page 37

Figure 20. Power-up timing (max) Program, Erase and Write commands are Rejected by the device Chip selection Not Allowed V CC (min) Reset State of the device V WI Table 8. Power-up timing and V Symbol ...

Page 38

... CC V Electrostatic discharge voltage (Human Body model) ESD 1. Compliant with JEDEC Std J-STD-020C (for small body, Sn- assembly), the Numonyx RoHS compliant 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU. 2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω) 38/57 ...

Page 39

DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC Characteristic tables that follow are derived from tests performed under the ...

Page 40

Table 14. DC characteristics Symbol Parameter I Input leakage current LI I Output leakage current LO I Standby current CC1 I Deep Power-down current CC2 I Operating current (READ) CC3 I Operating current (PP) CC4 I Operating current (WRSR) CC5 ...

Page 41

Table 15. AC characteristics (75 MHz operation) 75 MHz available only for products made in 110 nm technology, Test conditions specified in Symbol Alt. Clock frequency for the following instructions FAST_READ, PP, SE, BE, DP, RES, WREN, WRDI, ...

Page 42

Table 15. AC characteristics (75 MHz operation) (continued) 75 MHz available only for products made in 110 nm technology, Test conditions specified in Symbol Alt. t Write Status Register cycle time W Page Program cycle time (256 byte) Page Program ...

Page 43

Table 16. AC characteristics (25 MHz operation) Test conditions specified in Symbol Alt. Clock frequency for the following instructions FAST_READ, PP, SE, BE, DP, RES, WREN WRDI, RDSR, WRSR f Clock frequency for READ instructions R ...

Page 44

Figure 22. Serial input timing S tCHSL C tDVCH D High Impedance Q Figure 23. Write Protect setup and hold timing during WRSR when SRWD = 1 W tWHSL High Impedance Q 44/57 tSLCH tCHSH tCHDX tCLCH ...

Page 45

Figure 24. Hold timing HOLD Figure 25. Output timing S C tCLQV tCLQX tCLQX Q ADDR. D LSB IN tHLCH tCHHL tCHHH tHLQZ tHHQX tCH tCLQV tHHCH AI02032 tCL tSHQZ LSB OUT tQLQH tQHQL AI01449e 45/57 ...

Page 46

Package mechanical Figure 26. VFQFPN8 (MLP8) 8-lead Very thin Fine Pitch Quad Flat Package No lead, 6 × 5 mm, package outline Drawing is not to scale. 2. The circle in the top ...

Page 47

Figure 27. SO8 wide – 8 lead Plastic Small Outline, 208 mils body width, package outline Drawing is not to scale. 2. The ‘1’ that appears in the top view of the package shows ...

Page 48

Figure 28. SO8N – 8 lead Plastic Small Outline, 150 mils body width, package outline A2 1. Package is not to scale. Table 19. SO8N – 8 lead Plastic Small Outline, 150 mils body width, package mechanical data Symbol Typ ...

Page 49

Figure 29. PDIP8 – 8 lead Plastic Small Outline, 300 mils body width, package outline Package is not to scale. Table 20. PDIP8 – 8 lead Plastic Small Outline, 300 mils body width, package ...

Page 50

Figure 30. UFDFPN (MLP8) 8-lead ultra thin fine pitch dual flat package no lead, 4X3 mm package mechanical data 1. Drawing is not to scale. 50/57 ...

Page 51

Table 21. UFDFPN (MLP8) 8-lead ultra thin fine pitch dual flat package no lead, 4X3 mm package mechanical data Databook (mm) Symbol Typ Min A 0.55 0.45 A1 0.02 0.00 A3 — 0.127 θ — D2 0.80 0.70 E2 0.20 ...

Page 52

... QNEE9801. Please ask your Numonyx sales office for a copy. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. 52/57 Example: M25P80 – ...

Page 53

... Available only for Automotive product. Note: Numonyx strongly recommends the use of the Automotive Grade devices (Auto Grade 6 and automotive envirnoment. The high reliability certified flow (HRCF) is described in the quality note QNEE9801. Please ask your Numonyx sales office for a copy. M25P80 – (2) 6 ...

Page 54

... SHQZ Device grade 3 specifications removed from datasheet. Data retention conditions changed in Table 11: Data retention and Figure 3: Bus Master and memory devices on the SPI bus Note 2 added. Note 2 added below Figure 26 and Note on SO8 package removed below scheme ...

Page 55

... Table 15: AC characteristics (40 MHz operation, Grade 6) removed. Modified the maximum value for f (75 MHz 10-Dec-2007 16 Applied Numonyx branding. Added a reference to customer’s ability to request dedicated part number in Section 6.3: Read Identification (RDID) on page Moved specifications in “max” column to “min” column and changed the “ ...

Page 56

Table 24. Document revision history Date Revision 19-Feb-2009 19 3-August- 20 2009 2-Feb-2010 21 23-Feb-2010 22 14-April- 23 2010 56/57 Changes Made the followng changes: added a bullet to cover page, stating "Automotive Certified Parts Available" Revised part numbering, including ...

Page 57

... NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems nuclear facility Numonyx may make changes to specifications and product descriptions at any time, without notice. ...

Related keywords