M95512-RDW6P STMicroelectronics, M95512-RDW6P Datasheet - Page 13

IC EEPROM 512KBIT 2MHZ 8TSSOP

M95512-RDW6P

Manufacturer Part Number
M95512-RDW6P
Description
IC EEPROM 512KBIT 2MHZ 8TSSOP
Manufacturer
STMicroelectronics
Datasheet

Specifications of M95512-RDW6P

Format - Memory
EEPROMs - Serial
Memory Type
EEPROM
Memory Size
512K (64K x 8)
Speed
2MHz
Interface
SPI, 3-Wire Serial
Voltage - Supply
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Part Number:
M95512-RDW6P
Manufacturer:
ST
0
M95512-DR, M95512-W, M95512-R
4.1.4
4.2
4.3
Power-down
During power-down (continuous decrease in V
defined in
Active Power and Standby Power modes
When Chip Select (S) is low, the device is selected, and in the Active Power mode. The
device consumes I
When Chip Select (S) is high, the device is deselected. If a Write cycle is not currently in
progress, the device then goes in to the Standby Power mode, and the device consumption
drops to I
Hold condition
The Hold (HOLD) signal is used to pause any serial communications with the device without
resetting the clocking sequence.
During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data
Input (D) and Serial Clock (C) are Don’t Care.
To enter the Hold condition, the device must be selected, with Chip Select (S) low.
Normally, the device is kept selected, for the whole duration of the Hold condition.
Deselecting the device while it is in the Hold condition, has the effect of resetting the state of
the device, and this mechanism can be used if it is required to reset any processes that had
been in progress
The Hold condition starts when the Hold (HOLD) signal is driven low at the same time as
Serial Clock (C) already being low (as shown in
The Hold condition ends when the Hold (HOLD) signal is driven high at the same time as
Serial Clock (C) already being low.
Figure 6
with Serial Clock (C) being low.
1. This resets the internal logic, except the WEL and WIP bits of the Status Register.
2. In the specific case where the device has shifted in a Write command (Inst + Address + data bytes, each data
byte being exactly 8 bits), deselecting the device also triggers the write cycle of this decoded command.
deselected (Chip Select (S) should be allowed to follow the voltage applied on V
in Standby Power mode (that is there should not be any internal write cycle in
progress).
also shows what happens if the rising and falling edges are not timed to coincide
CC1
Table 8
.
(1)(2)
and
CC
, as specified in
.
Table
10), the device must be:
Doc ID 11124 Rev 14
Table
16.
CC
Figure
below the minimum V
6).
CC
Operating features
operating voltage
CC
13/48
)

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