M29W640GL70ZF6E NUMONYX, M29W640GL70ZF6E Datasheet

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M29W640GL70ZF6E

Manufacturer Part Number
M29W640GL70ZF6E
Description
IC FLASH 64MBIT 70NS 64TBGA
Manufacturer
NUMONYX
Series
Axcell™r
Datasheet

Specifications of M29W640GL70ZF6E

Format - Memory
FLASH
Memory Type
FLASH - Nor
Memory Size
64M (8Mx8, 4Mx16)
Speed
70ns
Interface
Parallel
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TBGA
Package
64TBGA
Cell Type
NOR
Density
64 Mb
Architecture
Sectored
Block Organization
Symmetrical
Typical Operating Supply Voltage
3|3.3 V
Sector Size
64KByte x 128
Timing Type
Asynchronous
Interface Type
Parallel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M29W640GL70ZF6E
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Part Number:
M29W640GL70ZF6E
Quantity:
162
Feature
Table 1.
October 2009
Supply voltage
– V
– V
Asynchronous random/page read
– Page width: 4 words
– Page access: 25 ns
– Random access: 60 ns, 70 ns, 90 ns
Fast program commands
– 2-word/4-byte program (without V
– 4-word/8-byte program (with V
– 16-word/32-byte write buffer
Programming time
– 10 μs per byte/word typical
– Chip program time: 10 s (4-word program)
Memory organization
– M29W640GH/L:
– M29W640GT/B
Program/erase controller
– Embedded byte/word program algorithms
Program/erase suspend and resume
– Read from any block during program
– Read and program another block during
128 main blocks, 64 Kbytes each
Eight 8-Kbyte boot blocks (top or bottom)
127 main blocks, 64 Kbytes each
suspend
erase suspend
CC
PP
64-Mbit (8 Mbit x8 or 4 Mbit x16, uniform block or boot block)
=12 V for fast program (optional)
= 2.7 to 3.6 V for program/erase/read
Device summary
M29W640GH: uniform, last block protected by V
M29W640GL: uniform, first block protected by V
M29W640GB: bottom boot blocks
M29W640GT: top boot blocks
Root part number
PP
=12 V)
PP
=12 V)
Rev 11
M29W640GH M29W640GL
M29W640GT M29W640GB
PP
PP
/WP
/WP
TFBGA48 (ZA)
RoHS compliant packages
128-word extended memory block
Low power consumption:standby and
automatic standby
Unlock Bypass Program command
– Faster production/batch programming
Common flash interface: 64-bit security code
V
Temporary block unprotection mode
100,000 program/erase cycles per block
Electronic signature
– Manufacturer code: 0020h
– Device code (see
Automotive Certified Parts Available
6 x 8 mm
PP
TSOP48 (NA)
FBGA
12 x 20 mm
/WP pin for fast program and write protect
1. Packages only available upon request.
3 V supply flash memory
FBGA64 (ZS)
11 x 13 mm
227Eh + 220Ch + 2201h
227Eh + 220Ch + 2200h
227Eh + 2210h + 2201h
227Eh + 2210h + 2200h
BGA
Table
Device code
1)
14 x 20 mm(1)
TSOP56 (NB)
www.numonyx.com
10 x 13 mm(1)
TBGA64 (ZF)
FBGA
1/90
1

Related parts for M29W640GL70ZF6E

M29W640GL70ZF6E Summary of contents

Page 1

... Electronic signature – Manufacturer code: 0020h – Device code (see Automotive Certified Parts Available /WP PP /WP PP Rev 11 TSOP56 (NB mm(1) FBGA BGA TBGA64 (ZF) FBGA64 (ZS mm(1) Table 1) Device code 227Eh + 220Ch + 2201h 227Eh + 220Ch + 2200h 227Eh + 2210h + 2201h 227Eh + 2210h + 2200h 1/90 www.numonyx.com 1 ...

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Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Chip Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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... Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Appendix A Block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Appendix B Common flash interface (CFI Appendix C Extended memory block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 C.1 Factory locked extended block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 C.2 Customer lockable extended block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Appendix D Block protection D.1 Programmer technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 D.2 In-system technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Appendix E Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 4/90 ...

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List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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... Description The M29W640G is a 64-Mbit (8 Mbit Mbit x16) non-volatile memory that can be read, erased and reprogrammed. These operations can be performed using a single low voltage (2.7 to 3.6V) supply. On power-up the memory defaults to its read mode. The memory is divided into blocks that can be erased independently possible to preserve valid data while old data is erased ...

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... The M29W640GT, M29W640GB, M29W640GH and M29W640GL, are offered in TSOP48 ( mm), TSOP56 ( mm), TFBGA48 ( mm, 0.8 mm pitch), and TBGA64 ( mm pitch) packages. The memory is delivered with all the bits erased (set to ‘1’). Figure 1. Logic diagram A0-A21 (1) Table 2 ...

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Table 3. Protection granularity on the M29W640GH and M29W640GL Block Kbytes/Kwords 64/ 64/ 120 to 123 4 x 64/32 124 to 127 4x 64/32 1. Used as the ...

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Figure 2. TSOP48 connections V PP /WP 10/90 A15 1 48 A14 A13 A12 A11 A10 A9 A8 A19 A20 M29W640GT M29W640GB A21 13 36 M29W640GH M29W640GL RB A18 A17 ...

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Figure 3. TSOP56 connections A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 M29W640GT M29W640GB W M29W640GH M29W640GL A21 RB A18 A17 ...

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Figure 4. TFBGA48 connections (top view through package 12/ A17 A18 A21 A1 A5 A20 A19 ...

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Figure 5. TBGA64 connections (top view through package ( Pads D8 ...

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... Address Inputs to include this pin when BYTE is Low except when stated explicitly otherwise. 2.5 Chip Enable (E) The Chip Enable, E, activates the memory, allowing bus read and bus write operations to be performed. When Chip Enable is High, V 2.6 Output Enable (G) The Output Enable, G, controls the bus read operation of the memory. ...

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... Write Enable (W) The Write Enable, W, controls the bus write operation of the memory’s command interface. 2.8 V /Write Protect (V PP The V /Write Protect pin provides two functions. The V PP use an external high voltage power supply to reduce the time required for Unlock Bypass Program operations ...

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Table 6. Hardware protection V / M29W640GT and V IH M29W640GH and V IL M29W640GT and V ID M29W640GH and 16/90 Last 2 blocks at ...

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... Byte/Word Organization Select (BYTE) The Byte/Word Organization Select pin is used to switch between the x8 and x16 bus modes of the memory. When Byte/Word Organization Select is Low mode, when it is High then the last and the first block in the M29W640GH and IL ...

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... This prevents bus write operations from accidentally damaging the data LKO during power-up, power-down and power surges. If the program/erase controller is programming or erasing during this time then the operation aborts and the memory contents being altered will be invalid. A 0.1 μF capacitor should be connected between the V ground pin to decouple the current surges from the power supply ...

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... See and VIL Table 8: Bus operations, BYTE = Chip Enable or Write Enable are ignored by the memory and do not affect bus operations. 3.1 Bus read Bus read operations read from the memory cells, or specific registers in the command interface ...

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... They require V applied to some pins. 3.6.1 Electronic signature The memory has two codes, the manufacturer code and the device code, that can be read to identify the memory. These codes can be read by applying the signals listed in Bus operations, BYTE = VIL 3.6.2 Block protect and chip unprotect Groups of blocks can be protected against accidental program or erase ...

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... Output disable Standby Read manufacturer code Read device code (cycle 1) Read device code (cycle Read device code (cycle 3) Read extended memory block verify code Read block protection status (1) IL Address Inputs DQ14- DQ15A–1, A0-A21 DQ8 Cell address Hi-Z IH Command address ...

Page 22

... IL IH Table 9. Read electronic signature addresses Code Manufacturer code Device code (cycle 1) Device code (cycle 2) Device code (cycle 3) Extended memory block verify code Block protection status other address bits set A12- A21 must be set to the block address. 22/90 (1) IH Address Inputs ...

Page 23

... The Read/Reset command can be issued, between bus write cycles before the start of a program or erase operation, to return the device to read mode. If the Read/Reset command is issued during the timeout of a block erase operation then the memory will take μs to abort. During the abort period no valid data can be read from the memory. The Read/Reset command will not abort an erase operation when issued while in erase suspend ...

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... When an error occurs the memory will continue to output the status register. A Read/Reset command must be issued to reset the error condition and return to read mode. The Chip Erase command sets all of the bits in unprotected blocks of the memory to ’1’. All previous data is lost. Refer to Figure 8: Chip/block erase waveforms (8-bit mode) AC waveforms ...

Page 25

... The program/erase controller will suspend within the erase suspend latency time of the Erase Suspend command being issued. Once the program/erase controller has stopped the memory will be set to read mode and the erase will be suspended. If the Erase Suspend command is issued during the period when the memory is waiting for an additional block (before the program/erase controller starts) then the erase is suspended immediately and will start immediately when the Erase Resume command is issued ...

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Erase Resume command The Erase Resume command must be used to restart the program/erase controller after an Erase Suspend. The device must be in read array mode before the Resume command will be accepted. An erase can be suspended ...

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... Note that the Program command cannot change a bit set to ’0’ back to ’1’. One of the erase commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’. Refer to Figure 6: Write enable controlled program waveforms (8-bit mode) Chip enable controlled program waveforms (8-bit mode) waveforms ...

Page 28

Fast program commands There are five fast program commands available to improve the programming throughput, by writing several adjacent words or bytes in parallel: Quadruple and Octuple Byte Program, available for x8 operations Double and Quadruple Word Program, available ...

Page 29

... Note that the fast program commands cannot change a bit set to ’0’ back to ’1’. One of the erase commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’. Typical program times are given in ...

Page 30

... Unlock Bypass Program command The Unlock Bypass command is used in conjunction with the Unlock Bypass Program command to program the memory. When the cycle time to the device is long, considerable time saving can be made by using these commands. Three bus write operations are required to issue the Unlock Bypass command. ...

Page 31

... Write to Buffer and Program operation possible to detect program operation fails when changing programmed data from ‘0’ to ‘1’, that is when reprogramming data in a portion of memory already programmed. The resulting data will be the logical OR between the previous value and the current value. ...

Page 32

... The extended block (with the same address as the boot blocks) cannot be erased, and can be treated as one-time programmable (OTP) memory. In extended block mode the boot blocks are not accessible. ...

Page 33

Block Protect and Chip Unprotect commands Groups of blocks can be protected against accidental program or erase. The protection groups are shown in and M29W640GT Table 30: Bottom boot block addresses, can be unprotected to allow the data inside ...

Page 34

Table 10. Commands, 16-bit mode, BYTE = V Command Addr Data Addr Data 1 X Read/Reset 3 555 Auto Select 3 555 Program 4 555 Double Word 3 555 Program Quadruple Word 5 555 Program Unlock Bypass 3 555 Unlock ...

Page 35

Table 11. Commands, 8-bit mode, BYTE = V Command 1st 2nd Add Data Add Data Add Data Add Data Add Data Add Data Add Data Add Data Add Data Read/Reset 3 AAA AA 555 55 Auto Select ...

Page 36

Table 12. Program, erase times and endurance cycles Parameter Chip Erase (4)(5) Block Erase (64 Kbytes) Erase Suspend Latency Time Program (byte or word) Double Byte Double Word /Quadruple Byte Program Quadruple Word / Octuple Byte Program (7) Single Byte ...

Page 37

... Only the third and fourth cycles of the Program command are represented. The Program command is followed by the check of status register data polling bit and by a read operation that outputs the data, D Program command address of the memory location to be programmed the data to be programmed. 3. DQ7 is the complement of the data bit being programmed to DQ7 (see 4. Addresses differ in x8 mode. ...

Page 38

... Only the third and fourth cycles of the Program command are represented. The Program command is followed by the check of status register data polling bit address of the memory location to be programmed the data to be programmed. 3. DQ7 is the complement of the data bit being programmed to DQ7 (see 4 ...

Page 39

Figure 8. Chip/block erase waveforms (8-bit mode) tAVAV A0-A20/ A–1 tAVWL tELWL E tGHWL G tWLWH W tDVWH DQ0-DQ7/ DQ8-DQ15 1. For a Chip Erase command, addresses and data are 555h and 10h, respectively, while they are BA and 30h ...

Page 40

... DQ7, not its complement. During erase operations the data polling bit outputs ’0’, the complement of the erased state of DQ7. After successful completion of the erase operation the memory returns to read mode. In erase suspend mode the data polling bit will output a ’1’ during a bus read operation within a block being erased. The data polling bit will change from a ’ ...

Page 41

... Note that the Program command cannot change a bit set to ’0’ back to ’1’ and attempting will set DQ5 to ‘1’. A bus read operation to that address will show the bit is still ‘0’. One of the erase commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’. ...

Page 42

Table 13. Status register bits Operation Address Program Any address Program During Erase Any address Suspend Write to Buffer and Any address Program Abort Write to Buffer and Any address Program Program Error Any address Chip Erase Any address Erasing ...

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Figure 9. Data polling flowchart START READ DQ5 & DQ7 at VALID ADDRESS DQ7 YES = DATA NO NO DQ5 = 1 YES READ DQ7 at VALID ADDRESS DQ7 YES = DATA NO FAIL PASS AI90194 43/90 ...

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Figure 10. Data toggle flowchart 44/90 START READ DQ6 READ DQ5 & DQ6 DQ6 NO = TOGGLE YES NO DQ5 = 1 YES READ DQ6 TWICE DQ6 NO = TOGGLE YES FAIL PASS AI90195B ...

Page 45

Maximum ratings Stressing the device above the rating listed in the cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. These are stress ratings only and operation of the ...

Page 46

DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristic tables that follow are derived from tests performed under the ...

Page 47

Table 16. Device capacitance Symbol Parameter C Input capacitance IN C Output capacitance OUT 1. Sampled only, not 100% tested. Table 17. DC characteristics Symbol Parameter (1) I Input leakage current LI I Output leakage current LO I Supply current ...

Page 48

Figure 13. Read mode AC waveforms (8-bit mode) A0-A20/ A– DQ0-DQ7/ DQ8-DQ15 BYTE tELBL/tELBH 1. Data are output on DQ0-DQ7. DQ8-DQ15 are Hi-Z. Figure 14. Page read AC waveforms (8-bit mode) A2-A20 A–1-A1 VALID tAVQV E tELQV G ...

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Table 18. Read AC characteristics Symbol Alt t t Address Valid to Next Address Valid AVAX Address Valid to Output Valid AVQV ACC t t Address Valid to Output Valid (Page) AVQV1 PAGE ( Chip ...

Page 50

Figure 15. Write AC waveforms, write enable controlled (8-bit mode) A0-A20/ A–1 E tELWL G tGHWL W DQ0-DQ7/ DQ8-DQ15 V CC tVCHEL RB 50/90 tAVAX VALID tAVWL tWLWH tDVWH VALID tWHRL tWLAX tWHEH tWHGL1 tWHWL tWHDX AI05560 ...

Page 51

Figure 16. Write AC waveforms, chip enable controlled (8-bit mode) A0-A20/ A–1 W tWLEL G tGHEL E DQ0-DQ7/ DQ8-DQ15 V CC tVCHWL RB tAVAV VALID tAVEL tELEH tDVEH VALID tEHRL tELAX tEHWH tEHGL1 tEHEL1 tEHDX AI05561 51/90 ...

Page 52

Table 19. Write AC characteristics Symbol Alt t t Address Valid to Next Address Valid AVAX Chip Enable Low to Write Enable Low ELWL Write Enable Low to Chip Enable Low WLEL WS t ...

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Figure 17. Reset/Block Temporary Unprotect AC waveforms tPLPX RP Figure 18. Accelerated program timing waveforms / tVHVPP Table 20. Reset/Block Temporary Unprotect AC characteristics Symbol Alt (1) ...

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Figure 19. Data polling AC waveforms tWHEH DQ7 DATA DQ6-DQ0 DATA R/B 1. DQ7 returns valid data bit when the ongoing Program or Erase command is completed. 2. See Table 21: Data polling and data toggle AC ...

Page 55

Table 21. Data polling and data toggle AC characteristics Symbol Alt Address setup time to Output Enable Low t t AXGL ASO during toggle bit polling t Address hold time from Output Enable during GHAX t AHT toggle bit polling ...

Page 56

... Package mechanical To meet environmental requirements, Numonyx offers these devices in RoHS compliant packages, which are lead-free. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ...

Page 57

Figure 22. TSOP56 – 56 lead plastic thin small outline package outline, top view DIE 1. Drawing is not to scale. Table 23. TSOP56 – 56 lead plastic thin small outline ...

Page 58

Figure 23. TFBGA48 mm active ball array, 0.8 mm pitch, package outline, bottom view FD FE BALL "A1" Drawing is not to scale. Table 24. TFBGA48 ...

Page 59

Figure 24. TBGA64 mm active ball array pitch, package outline, bottom view BALL "A1" Drawing is not to scale. Table 25. TBGA64 ...

Page 60

Figure 25. FBGA64 active ball array pitch, package outline, bottom view BALL "A1" Drawing is not to scale. Table 26. FBGA64 ...

Page 61

... F = RoHS package, tape & reel packing 1. Packages only available upon request. Note: This product is also available with the extended block factory locked. For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest Numonyx sales office. M29W640GT /WP PP /WP ...

Page 62

Appendix A Block addresses Table 28. M29W640GH and M29W640GL block addresses Block Kbytes/Kwords 0 64/32 1 64/32 2 64/32 3 64/32 4 64/32 5 64/32 6 64/32 7 64/32 8 64/32 9 64/32 10 64/32 11 64/32 12 64/32 13 ...

Page 63

Table 28. M29W640GH and M29W640GL block addresses (continued) Block Kbytes/Kwords Protection block group 32 64/32 33 64/32 Protection group 34 64/32 35 64/32 36 64/32 37 64/32 Protection group 38 64/32 39 64/32 40 64/32 41 64/32 Protection group 42 ...

Page 64

Table 28. M29W640GH and M29W640GL block addresses (continued) Block Kbytes/Kwords 64 64/32 65 64/32 66 64/32 67 64/32 68 64/32 69 64/32 70 64/32 71 64/32 72 64/32 73 64/32 74 64/32 75 64/32 76 64/32 77 64/32 78 64/32 ...

Page 65

Table 28. M29W640GH and M29W640GL block addresses (continued) Block Kbytes/Kwords Protection block group 96 64/32 97 64/32 Protection group 98 64/32 99 64/32 100 64/32 101 64/32 Protection group 102 64/32 103 64/32 104 64/32 105 64/32 Protection group 106 ...

Page 66

Table 29. Top boot block addresses, M29W640GT Block Kbytes/Kwords Protection block group 0 64/32 1 64/32 2 64/32 3 64/32 4 64/32 5 64/32 6 64/32 7 64/32 8 64/32 9 64/32 10 64/32 11 64/32 12 64/32 13 64/32 ...

Page 67

Table 29. Top boot block addresses, M29W640GT (continued) Block Kbytes/Kwords Protection block group 32 64/32 33 64/32 Protection group 34 64/32 35 64/32 36 64/32 37 64/32 Protection group 38 64/32 39 64/32 40 64/32 41 64/32 Protection group 42 ...

Page 68

Table 29. Top boot block addresses, M29W640GT (continued) Block Kbytes/Kwords Protection block group 64 64/32 65 64/32 66 64/32 67 64/32 68 64/32 69 64/32 70 64/32 71 64/32 72 64/32 73 64/32 74 64/32 75 64/32 76 64/32 77 ...

Page 69

Table 29. Top boot block addresses, M29W640GT (continued) Block Kbytes/Kwords Protection block group 96 64/32 97 64/32 Protection group 98 64/32 99 64/32 100 64/32 101 64/32 Protection group 102 64/32 103 64/32 104 64/32 105 64/32 Protection group 106 ...

Page 70

Table 29. Top boot block addresses, M29W640GT (continued) Block Kbytes/Kwords Protection block group 131 8/4 132 8/4 133 8/4 134 8/4 1. Used as the extended block addresses in extended block mode. Table 30. Bottom boot block addresses, M29W640GB Block ...

Page 71

Table 30. Bottom boot block addresses, M29W640GB (continued) Block Kbytes/Kwords Protection block group 27 64/32 28 64/32 Protection group 29 64/32 30 64/32 31 64/32 32 64/32 Protection group 33 64/32 34 64/32 35 64/32 36 64/32 Protection group 37 ...

Page 72

Table 30. Bottom boot block addresses, M29W640GB (continued) Block Kbytes/Kwords 59 64/32 60 64/32 61 64/32 62 64/32 63 64/32 64 64/32 65 64/32 66 64/32 67 64/32 68 64/32 69 64/32 70 64/32 71 64/32 72 64/32 73 64/32 ...

Page 73

Table 30. Bottom boot block addresses, M29W640GB (continued) Block Kbytes/Kwords Protection block group 91 64/32 92 64/32 Protection group 93 64/32 94 64/32 95 64/32 96 64/32 Protection group 97 64/32 98 64/32 99 64/32 100 64/32 Protection group 101 ...

Page 74

Table 30. Bottom boot block addresses, M29W640GB (continued) Block Kbytes/Kwords 123 64/32 124 64/32 125 64/32 126 64/32 127 64/32 128 64/32 129 64/32 130 64/32 131 64/32 132 64/32 133 64/32 134 64/32 1. Used as the extended block ...

Page 75

... The CFI data structure also contains a security area where a 64- bit unique security number is written (see accessed only in read mode by the final user impossible to change the security number after it has been written by Numonyx. Table 31. Query structure overview ...

Page 76

Table 33. CFI query system interface information Address Data x16 x8 V logic supply minimum program/erase voltage CC 1Bh 36h 0027h bit 7 to 4BCD value in volts bit 3 to 0BCD value in 100 mV V logic supply maximum ...

Page 77

Table 34. Device geometry definition Address Data x16 x8 27h 4Eh 0017h 28h 50h 0002h 29h 52h 0000h 2Ah 54h 0005h 2Bh 56h 0000h M29W640GH, M29W640GL 2Ch 58h M29W640GT, M29W640GB 2Dh 5Ah 2Eh 5Ch M29W640GH, M29W640GL 2Fh 5Eh 30h 60h ...

Page 78

Table 35. Primary algorithm-specific extended query table Address Data x16 x8 40h 80h 0050h 41h 82h 0052h Primary algorithm extended query table unique ASCII string ‘PRI’ 42h 84h 0049h 43h 86h 0031h Major version number, ASCII 44h 88h 0033h Minor ...

Page 79

Table 36. Security code area Address Data x16 x8 61h C3h, C2h XXXX 62h C5h, C4h XXXX 63h C7h, C6h XXXX 64h C9h, C8h XXXX Description 64 bit: unique device number 79/90 ...

Page 80

... Bit DQ7 is the most significant bit in the extended block verify code and a specific procedure must be followed to read it. See ‘extended memory block verify code operations, BYTE = VIL bit DQ7. ...

Page 81

Table 37. Extended block address and data Address x8 x16 000000h-00007Fh 000000h-00003Fh 000080h-0000FFh 000040h-00007Fh Data Factory locked Customer lockable Security identification number Unavailable Determined by customer 81/90 ...

Page 82

... Appendix D Block protection Block protection can be used to prevent any operation from modifying the data stored in the memory. The blocks are protected in groups, refer to and Table 29 Table 30 erase operations within the protected group fail to change the data. There are three techniques that can be used to control block protection, these are the programmer technique, the in-system technique and temporary unprotection. Temporary unprotection is controlled by the Reset/Block Temporary Unprotection pin, RP ...

Page 83

Table 38. Programmer technique bus operations, BYTE = V Operation E G Block (Group ( Protect Chip Unprotect Block (Group Protection Verify Block (Group) ...

Page 84

Figure 26. Programmer equipment group protect flowchart 1. Block protection groups are shown in 84/90 START ADDRESS = GROUP ADDRESS Wait 4µs W ...

Page 85

Figure 27. Programmer equipment chip unprotect flowchart ADDRESS = CURRENT GROUP ADDRESS NO ++n = 1000 YES FAIL 1. Block protection groups are shown in START PROTECT ALL GROUPS n = ...

Page 86

Figure 28. In-system equipment group protect flowchart 2. Block protection groups are shown can be either at V 86/90 START WRITE 60h ADDRESS = GROUP ADDRESS A0, A2, A3, A6 ...

Page 87

Figure 29. In-system equipment chip unprotect flowchart ADDRESS = CURRENT GROUP ADDRESS ADDRESS = CURRENT GROUP ADDRESS ++ 1000 YES ISSUE READ/RESET COMMAND FAIL 1. Block protection groups are shown in START PROTECT ALL ...

Page 88

Appendix E Flowchart Figure 30. Write to Buffer and Program flowchart and pseudocode 1. n+1 is the number of addresses to be programmed Write to Buffer and Program Abort and Reset must be issued to return the device ...

Page 89

... Table 13: Status Register bits 22-Feb-2007 access time added. 27-Mar-2008 5 Applied Numonyx branding. Updated: Section 2.9: Reset/Block Temporary Unprotect 09-Jun-2008 6 protection. Minor text changes. Added the following: – To cover page, bullet stating: Automotive Certified Parts Available for Version 16-Dec-2008 7 M29W640GT/M29W640GB ...

Page 90

... NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems nuclear facility Numonyx may make changes to specifications and product descriptions at any time, without notice. ...

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