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N25Q128A11TF840F
N25Q128A11TF840F | |
|---|---|
| Manufacturer Part Number | N25Q128A11TF840F |
| Description | IC SRL FLASH 128MB NMX 8-VDFPN |
| Manufacturer | NUMONYX |
| Series | Forté™ |
| N25Q128A11TF840F datasheets |
|
Availability: By request
International delivery:
Warranty: 60 days
×
- We provide standard 60-days warranty for all parts. If warranty differs we always mention it beforehand. In case of return we cover shipping costs.
- If you still have any questions - please contact us
×
Shipping terms
- Standard delivery time differs from 5-8 business days if the supplier is a local one to 12-14 days if the suplier is from overseas. If delivery time differs it's always mentioned in our quotation.
- We ship worldwide using main international couriers like FedEx, DHL, UPS, TNT, EMS. We can also use client's freight account. Other shipping methods can be discussed. We do best to meet your needs!
Payment terms
- For new client payment term is payment in advance. At this moment we accept 3 payment methods: wire transfer, PayPal and Western Union. Credit card payment is under constrution and will be introduced soon. Escrow service is acceptable. Net terms for regular customers is not a problem. Working with us is totally safe for you.
- If you still have any questions - please contact us
Specifications of N25Q128A11TF840F | |||
|---|---|---|---|
| Format - Memory | FLASH | Memory Type | FLASH |
| Memory Size | 128M (16M x 8) | Speed | 108MHz |
| Interface | SPI, 3-Wire Serial | Voltage - Supply | 1.7 V ~ 2 V |
| Operating Temperature | -40°C ~ 85°C | Package / Case | * |
| Lead Free Status / RoHS Status | Lead free / RoHS Compliant | ||
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PrevNext
Figure 43. Release from Deep Power-down instruction sequence
S
0
1
2
C
Instruction
DQ0
High Impedance
DQ1
9.2
DIO-SPI Instructions
In DIO-SPI protocol, instructions, addresses and input/Output data always run in parallel on
two wires: DQ0 and DQ1.
In the case of a Dual Command Fast Read (DCFR), Read OTP (ROTP), Read Lock
Registers (RDLR), Read Status Register (RDSR), Read Flag Status Register (RFSR), Read
NV Configuration Register (RDNVCR), Read Volatile Configuration Register (RDVCR),
Read Volatile Enhanced Configuration Register (RDVECR) and Read Identification (RDID)
instruction, the shifted-in instruction sequence is followed by a data-out sequence. Chip
Select (S) can be driven High after any bit of the data-out sequence is being shifted out.
In the case of a Dual Command Page Program (DCPP), Program OTP (POTP), Subsector
Erase (SSE), Sector Erase (SE), Bulk Erase (BE), Program/Erase Suspend (PES),
Program/Erase Resume (PER), Write Status Register (WRSR), Clear Flag Status Register
(CLFSR), Write to Lock Register (WRLR), Write Configuration Register (WRVCR), Write
Enhanced Configuration Register (WRVECR), Write NV Configuration Register
(WRNVCR), Write Enable (WREN) or Write Disable (WRDI) instruction, Chip Select (S)
must be driven High exactly at a byte boundary, otherwise the instruction is rejected, and is
not executed.
All attempts to access the memory array during a Write Status Register cycle, a Write Non
Volatile Configuration Register, a Program cycle or an Erase cycle are ignored, and the
internal Write Status Register cycle, Write Non Volatile Configuration Register, Program
cycle or Erase cycle continues unaffected, the only exception is the Program/Erase
Suspend instruction (PES), that can be used to pause all the program and the erase cycles
but the Program OTP (POT),, Bulk Erase (BE) and Write Non Volatile Configuration
Register. The suspended program or erase cycle can be resumed by mean of the
Program/Erase Resume instruction (PER). During the program/erase cycles also the polling
instructions (to check if the internal modify cycle is finished by mean of the WIP bit of the
Status Register or of the Program/Erase controller bit of the Flag Status register) are also
accepted to allow the application checking the end of the internal modify cycles, of course
these polling instructions don't affect the internal cycles performing.
t
3
4
5
6
7
RDP
Deep power-down mode
Standby mode
AI13745
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