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N25Q128A11TF840F
N25Q128A11TF840F | |
|---|---|
| Manufacturer Part Number | N25Q128A11TF840F |
| Description | IC SRL FLASH 128MB NMX 8-VDFPN |
| Manufacturer | NUMONYX |
| Series | Forté™ |
| N25Q128A11TF840F datasheets |
|
Availability: By request
International delivery:
Warranty: 60 days
×
- We provide standard 60-days warranty for all parts. If warranty differs we always mention it beforehand. In case of return we cover shipping costs.
- If you still have any questions - please contact us
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Shipping terms
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Specifications of N25Q128A11TF840F | |||
|---|---|---|---|
| Format - Memory | FLASH | Memory Type | FLASH |
| Memory Size | 128M (16M x 8) | Speed | 108MHz |
| Interface | SPI, 3-Wire Serial | Voltage - Supply | 1.7 V ~ 2 V |
| Operating Temperature | -40°C ~ 85°C | Package / Case | * |
| Lead Free Status / RoHS Status | Lead free / RoHS Compliant | ||
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Table 24.
Instruction set: QIO-SPI protocol (page 2 of 2)
Instruction
Description
WRNVCR
Write NV Configuration Register
RDVCR
Read Volatile Configuration Register 1000 0101
WRVCR
Write Volatile Configuration Register 1000 0001
Read Volatile Enhanced
RDVECR
Configuration Register
Write Volatile Enhanced
WRVECR
Configuration Register
DP
Deep Power-down
RDP
Release from Deep Power-down
The number of Dummy Clock cycles is configurable by the use
1)
SSE is only available in devices with Bottom or Top architecture
2)
9.3.1
Multiple I/O Read Identification (MIORDID)
The Multiple Input/Output Read Identification (MIORDID) instruction allows to read the
device identification data in the QIO-SPI protocol:
Manufacturer identification (1 byte)
Device identification (2 bytes)
Unlike the RDID instruction of the Extended SPI protocol, the Multiple Input/Output
instruction can not read the Unique ID code (UID) (17 bytes).
For further details on the manufacturer and device identification codes, see
Identification
(RDID).
Any Multiple Input/Output Read Identification (MIORDID) instruction while an Erase or
Program cycle is in progress, is not decoded, and has no effect on the cycle that is in
progress.
The device is first selected by driving Chip Select (S) Low. Then, the 8-bit instruction code
for the instruction is shifted in parallel on the 4 pins DQ0, DQ1, DQ2 and DQ3. After this, the
24-bit device identification, stored in the memory, will be shifted out on again in parallel on
DQ0, DQ1, DQ2 and DQ3. The identification bits are shifted out 4 at a time during the falling
edge of Serial Clock (C).
The Read Identification (RDID) instruction is terminated by driving Chip Select (S) High at
any time during data output.
When Chip Select (S) is driven High, the device is put in the Standby Power mode. Once in
the Standby Power mode, the device waits to be selected, so that it can receive, decode and
execute instructions.
Multiple I/O Read Identification (MIORDID) instruction sequence and data-out sequence
QIO-SPI.
134/185
One-byte
One-byte
Instruction
Address
Instruction
Code
bytes
Code (BIN)
(HEX)
1011 0001
B1h
0
85h
0
81h
0
0110 0101
65h
0
0110 0001
61h
0
1011 1001
B9h
0
1010 1011
ABh
0
r.
Dummy
Data
clock
bytes
cycle
0
2
∞
0
1 to
0
1
∞
0
1 to
0
1
0
0
0
0
9.1.1: Read
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