N25Q128A11TF840F

Manufacturer Part NumberN25Q128A11TF840F
DescriptionIC SRL FLASH 128MB NMX 8-VDFPN
ManufacturerNUMONYX
SeriesForté™
N25Q128A11TF840F datasheets

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Specifications of N25Q128A11TF840F

Format - MemoryFLASHMemory TypeFLASH
Memory Size128M (16M x 8)Speed108MHz
InterfaceSPI, 3-Wire SerialVoltage - Supply1.7 V ~ 2 V
Operating Temperature-40°C ~ 85°CPackage / Case*
Lead Free Status / RoHS StatusLead free / RoHS Compliant  
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Page 24/185

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5.1.5
Quad Input Fast Program
The Quad Input Fast Program (QIFP) instruction makes it possible to program up to 256
bytes using 4 input pins at the same time (by changing bits from 1 to 0).
For optimized timings, it is recommended to use the QIFP instruction to program all
consecutive targeted bytes in a single sequence rather than using several QIFP sequences
each containing only a few bytes.
5.1.6
Quad Input Extended Fast Program
The Quad Input Extended Fast Program (QIEFP) instruction is an enhanced version of the
Quad Input Fast Program instruction, allowing parallel input on the 4 input pins, including
the address being sent to the device.
For optimized timings, it is recommended to use the QIEFP instruction to program all
consecutive targeted bytes in a single sequence rather than using several QIEFP
sequences each containing only a few bytes.
5.1.7
Subsector erase, sector erase and bulk erase
The page program (PP) instruction allows bits to be reset from ‘1’ to’0’. In order to do this the
bytes of memory need to be erased to all 1s (FFh).
This can be achieved as follows:
a subsector at a time, using the subsector erase (SSE) instruction (only available on
the 8 boot sectors at the bottom or top addressable area of a device with a dedicated
part number); See
a sector at a time, using the sector erase (SE) instruction;
throughout the entire memory, using the bulk erase (BE) instruction.
This starts an internal erase cycle (of duration t
be preceded by a write enable (WREN) instruction.
5.1.8
Polling during a write, program or erase cycle
A further improvement in the time to Write Status Register (WRSR), POTP, PP,
DIFP,DIEFP,QIFP, QIEFP or Erase (SSE, SE or BE) can be achieved by not waiting for the
worst case delay (tW, tPP, tSSE, tSE, or tBE). The application program can monitor if the
required internal operation is completed, by polling the dedicated register bits to establish
when the previous Write, Program or Erase cycle is complete.
The information on the memory being in progress for a Program, Erase, or Write instruction
can be checked either on the Write In Progress (WIP) bit of the Status Register or in the
Program/Erase Controller bit of the Flag Status Register.
Note:
The Program/Erase Controller bit is the opposite state of the WIP bit in the Status Register.
In the Flag Status Register additional information can be checked, as eventual
Program/Erase failures by mean of the Program or erase Error bits.
5.1.9
Active power and standby power modes
When Chip Select (S) is Low, the device is selected, and in the active power mode.
24/185
Section 16: Ordering
information;
, t
SSE
SE
or t
). The erase instruction must
BE

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