N25Q128A11TF840F

Manufacturer Part NumberN25Q128A11TF840F
DescriptionIC SRL FLASH 128MB NMX 8-VDFPN
ManufacturerNUMONYX
SeriesForté™
N25Q128A11TF840F datasheets

Availability: By request

International delivery:

Warranty: 60 days

Shipping & payment terms

Added to cart

 

Specifications of N25Q128A11TF840F

Format - MemoryFLASHMemory TypeFLASH
Memory Size128M (16M x 8)Speed108MHz
InterfaceSPI, 3-Wire SerialVoltage - Supply1.7 V ~ 2 V
Operating Temperature-40°C ~ 85°CPackage / Case*
Lead Free Status / RoHS StatusLead free / RoHS Compliant  
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
Page 91
92
Page 92
93
Page 93
94
Page 94
95
Page 95
96
Page 96
97
Page 97
98
Page 98
99
Page 99
100
Page 100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
Page 98/185

Download datasheet (6Mb)Embed
PrevNext
Figure 27. Subsector Erase instruction sequence
S
0
C
DQ0
9.1.18
Sector Erase (SE)
The Sector Erase (SE) instruction sets to '1' (FFh) all bits inside the chosen sector. Before it
can be accepted, a Write Enable (WREN) instruction must previously have been executed.
After the Write Enable (WREN) instruction has been decoded, the device sets the Write
Enable Latch (WEL).
The Sector Erase (SE) instruction is entered by driving Chip Select (S) Low, followed by the
instruction code, and three address bytes on Serial Data input (DQ0). Any address inside
the sector is a valid address for the Sector Erase (SE) instruction. Chip Select (S) must be
driven Low for the entire duration of the sequence.
Chip Select (S) must be driven High after the eighth bit of the last address byte has been
latched in, otherwise the Sector Erase (SE) instruction is not executed. As soon as Chip
Select (S) is driven High, the self-timed Sector Erase cycle (whose duration is tSE) is
initiated. While the Sector Erase cycle is in progress, the Status Register may be read to
check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1
during the self-timed Sector Erase cycle, and is 0 when it is completed. At some unspecified
time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
A Sector Erase (SE) instruction applied to a page which is protected by the Block Protect
(BP3, BP2, BP1, BP0 and TB) bits is not executed.
A Sector Erase cycle can be paused by mean of Program/Erase Suspend (PES) instruction
and resumed by mean of Program/Erase Resume (PER) instruction.
98/185
1
2
3
4
5
6
7
8
9
Instruction
24 Bit Address
23 22
MSB
29 30 31
2
1
0
Subsector_Erase