M29W128GL70N6E NUMONYX, M29W128GL70N6E Datasheet
M29W128GL70N6E
Specifications of M29W128GL70N6E
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M29W128GL70N6E Summary of contents
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... Minimum 100,000 program/erase cycles per block RoHS compliant packages Automotive device grade: Temperature -40 °C to 125 °C (Automotive grade certified) /WP PP /WP PP Rev 11 M29W128GH M29W128GL 3 V supply flash memory BGA BGA TBGA64 (ZA) FBGA (ZS Device code 227Eh + 2221h + 2201h 227Eh + 2221h + 2200h www.numonyx.com 1/94 1 ...
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... Output disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.4 Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.5 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.6 Automatic standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.7 Auto select mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.7.1 Read electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.7.2 Verify extended memory block protection indicator . . . . . . . . . . . . . . . . 19 3.7.3 Verify block protection status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.7.4 Hardware block protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4 Hardware protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2/94 WP PP/ supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 ...
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... Unlock Bypass Chip Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.2.10 Unlock Bypass Write to Buffer Program command . . . . . . . . . . . . . . . . 38 6.2.11 Unlock Bypass Enhanced Buffered Program command . . . . . . . . . . . . 38 6.2.12 Unlock Bypass Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.3 Protection commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.3.1 Enter Extended Memory Block command . . . . . . . . . . . . . . . . . . . . . . . 41 6.3.2 Exit Extended Memory Block command . . . . . . . . . . . . . . . . . . . . . . . . 42 6.3.3 Lock register command set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3/94 ...
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... Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 10 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 11 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Appendix A Block addresses and read/modify protection groups . . . . . . . . . . 79 Appendix B Common flash interface (CFI Appendix C Extended memory block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 C.1 Factory locked extended memory block . . . . . . . . . . . . . . . . . . . . . . . . . . 88 C.2 Customer lockable extended memory block . . . . . . . . . . . . . . . . . . . . . . . 89 Appendix D Flowcharts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 4/94 ...
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Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Table 36. Query structure overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Table 37. CFI query identification string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Table 38. CFI query system interface information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Table 39. Device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Table 40. Primary algorithm-specific extended query table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Table 41. Security code area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Table 42. Extended memory block address and data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Table 43. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 6/94 ...
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List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... The M29W128GH and M29W128GL support asynchronous random read and page read from all blocks of the memory array. The devices also feature a write to buffer program capability that improves the programming throughput by programming in one shot a buffer of 32 words/64 bytes. The enhanced buffered program feature is also available to speed up the programming throughput, allowing to program 256 words in one shot (only in x16 mode) ...
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Table 2. Signal names Name A0-A22 Address inputs DQ0-DQ7 Data inputs/outputs DQ8-DQ14 Data inputs/outputs DQ15A 1 Data input/output or address input E Chip enable G Output enable W Write enable RP Reset RB Ready/busy output BYTE Byte/word organization select V ...
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Figure 2. TSOP connections V PP /WP 10/ A22 A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 M29W128GH 15 42 A21 M29W128GL RB A18 A17 ...
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Figure 3. TBGA and FBGA connections (top view through package CCQ ...
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Figure 4. Block addresses (x8) Address lines A22-A0, DQ15A-1 FFFFFFh 128 Kbytes 03FFFFh 128 Kbytes 020000h 01FFFFh 128 Kbytes 000000h 12/94 (x16) Address lines A22-A0 7FFFFFh 64 Kwords 64 Kwords 00FFFFh 64 Kwords 000000h Total of 128 uniform blocks AI13332 ...
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... Chip enable (E) The chip enable pin, E, activates the memory, allowing bus read and bus write operations to be performed. When chip enable is High, V 2.6 Output enable (G) The output enable pin, G, controls the bus read operation of the memory ...
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... Figure 24: Accelerated program timing Never raise V /write protect memory may be left in an indeterminate state. A 0.1 µF capacitor should be connected between the V /write protect pin and the V PP from the power supply. The PCB track widths must be sufficient to carry the currents required during unlock bypass program (see I characteristics) ...
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... The use of an open-drain output allows the ready/busy pins from several memories to be connected to a single pull-up resistor. A Low will then indicate that one, or more, of the memories is busy. 2.11 Byte/word organization select (BYTE used to switch between the x8 and x16 bus modes of the memory. When byte/word organization select is Low x16 mode. 2.12 V ...
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V ground the reference for all voltage measurements. The device features two V SS which must be connected to the system ground. 16/94 pins both of SS ...
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... The data inputs/outputs are in the high impedance state when output enable is High, V 3.4 Standby Driving chip enable High in read mode, causes the memory to enter standby mode and the data inputs/outputs pins are placed in the high-impedance state. To reduce the supply current to the standby supply current, I ...
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... In this case, it returns to the erase or program suspend mode. 3.7.1 Read electronic signature The memory has two codes, the manufacturer code and the device code used to identify the memory. These codes can be accessed by performing read operations with control signals and addresses set as shown in 18/94 ...
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... It can be read in auto select mode using either the programmer (see method (see Table 10 The protection status of the extended memory block is then output on bit DQ7 of the data input/outputs (see 3.7.3 Verify block protection status ...
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M Table 4. Bus operations, 8-bit mode (1) Operation E G Bus read Bus write Standby Output disable Reset ...
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Table 6. Read electronic signature - auto select mode - programmer method (8-bit mode) Read (1) cycle A22-A10 A9 Manufacture r code Device code (cycle Device code (cycle 2) ...
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... BAd any address in the block When using the in-system method, applying V Table 9. Block protection - auto select mode - programmer method (16-bit mode) (1) Operation E G Verify M29W128GL extended memory block M29W128GH V V indicator IL IL (bit DQ7) Verify block protection status BAd any address in the block. ...
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... The non-volatile and password protection modes both provide non-volatile protection. Volatilely protected blocks and non-volatilely protected blocks can co-exist within the memory array. However, the volatile protection only control the protection scheme for blocks that are not protected using the non-volatile or password protection. ...
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Volatile protection mode The volatile protection allows the software application to easily protect blocks against inadvertent change. However, the protection can be easily disabled when changes are needed. Volatile protection bits, VPBs, are volatile and unique for each block ...
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Refer to Table 19: Block protection status details on the block protection mechanism, and to volatile protection mode command set. 5.2.2 Non-volatile protection bit lock bit The non-volatile protection bit lock bit (NVPB lock bit global volatile bit ...
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Figure 5. Software protection scheme Parameter block or main block Volatile protection Non-volatile protection 1. NVPBs default to ‘1’ (block unprotected) after power-up and hardware reset. A block is protected or unprotected when its NVPB is set to ‘0’ and ...
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... The Read/Reset command can be issued, between bus write cycles before the start of a program or erase operation, to return the device to read mode. If the Read/Reset command is issued during the timeout of a block erase operation, the memory will take µs to abort. During the abort period no valid data can be read from the memory. ...
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... Table 41 (CFI) memory area. The Read CFI Query command is used to put the memory in read CFI query mode. Once in read CFI query mode, bus read operations to the memory will output data from the common flash interface (CFI) memory area. One bus write cycle is required to issue the Read CFI Query command ...
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... Resume command will be accepted. During erase suspend a bus read operation to the extended memory block will output the extended memory block data. Once in the extended block mode, the Exit Extended Block command must be issued before the erase operation can be resumed. ...
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... The Program Suspend command may also be issued during a program operation while an erase is suspended. In this case, data may be read from any addresses not in erase suspend or program suspend read is needed from the extended memory block area (one-time program area), the user must use the proper command sequences to enter and exit this region ...
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... Program command The Program command can be used to program a value to one address in the memory array at a time. The command requires four bus write operations, the final write operation latches the address and data in the internal state machine and starts the program/erase controller ...
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... Table 10. Standard commands, 8-bit mode (1) Command 1 Read/Reset 3 Manufacturer code Device code Extended memory Auto 3 block protection Select indicator Block protection status (5) Program 4 Chip Erase 6 Block Erase 6+ Erase/Program Suspend 1 Erase/Program Resume 1 Read CFI Query 1 1. The device doesn’t tolerate FFh as a valid command, and once FFh is issued to the device, the M29W128G will enter unexpected state. Adding a F0h command systematically after FFh command is necessary don’ ...
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... Table 11. Standard commands, 16-bit mode (1) Command 1 Read/Reset 3 Manufacturer code Device code Extended memory Auto 3 block protection Select indicator Block protection status (5) Program 4 Chip Erase 6 Block Erase 6+ Erase/Program Suspend 1 Erase/Program Resume 1 Read CFI Query 1 1. The device doesn’t tolerate FFh as a valid command, and once FFh is issued to the device, the M29W128G will enter unexpected state. Adding a F0h command systematically after FFh command is necessary don’ ...
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... After the fast program operation has completed, the memory will return to read mode, unless an error has occurred. When an error occurs bus read operations to the memory will continue to output the status register. A Read/Reset command must be issued to reset the error condition and return to read mode. One of the erase commands must be used to set all the bits in a block or in the whole memory from ’ ...
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... The status register bits DQ1, DQ5, DQ6, DQ7 can be used to monitor the device status during a write to buffer program operation possible to detect program operation fails when changing programmed data from ‘0’ to ‘1’, that is when reprogramming data in a portion of memory already programmed. See Appendix ...
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... It is possible to detect program operation fails when changing programmed data from ‘0’ to ‘1’, that is when reprogramming data in a portion of memory already programmed. The resulting data will be the logical OR between the previous and the current value. See Appendix D and a suggested flowchart on using the Enhanced Buffered Program command. ...
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... Unlock Bypass Program command The Unlock Bypass Program command can be used to program one address in the memory array at a time. The command requires two bus write operations, the final write operation latches the address and data and starts the program/erase controller. ...
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... Unlock Bypass Chip Erase command The Unlock Bypass Chip Erase command can be used to erase all memory blocks at a time. The command requires two bus write operations only instead of six using the standard Chip Erase command. The final bus write operation starts the program/erase controller. ...
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Unlock Bypass Reset command The Unlock Bypass Reset command can be used to return to read/reset mode from unlock bypass mode. Two bus write operations are required to issue the Unlock Bypass Reset command. Read/Reset command does not exit ...
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Table 13. Fast program commands, 16-bit mode 1st Command Add Write to Buffer N+5 555 Program Write to Buffer BAd 1 (5) Program Confirm Buffered Program 3 555 Abort and Reset Unlock Bypass 3 555 Unlock Bypass 2 X Program ...
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... Once the device is in the extended block mode, the extended memory block is addressed by using the addresses occupied by block 0 in the other operating modes (see addresses) ...
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... Exit Extended Memory Block command The Exit Extended Memory Block command is used to exit from the extended memory block mode and return the device to read mode. Four bus write operations are required to issue the command. 6.3.3 Lock register command set The M29W128GL and M29W128GH offer a set of commands to access the lock register and to configure and verify its content ...
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Password Read command The Password Read command is used to verify the password used in password protection mode. To verify the 64-bit password, the complete command sequence must be entered eight times at eight consecutive addresses selected by A1-A0 plus ...
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Figure 6. NVPB program/erase algorithm 44/94 Enter NVPB command set. Program NVPB Addr = BAd Read Byte twice Addr = BAd NO DQ6= Toggle YES NO DQ5=1 Wait 500 μs YES Read Byte twice Addr = BAd NO DQ6= Read ...
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NVPB lock bit command set Enter NVPB Lock Bit Command Set command Three bus write cycles are required to issue the Enter NVPB Lock Bit Command Set command. Once the command has been issued, the commands allowing to set ...
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Table 15. Block protection commands, 8-bit mode Command 1st 2nd Ad Data Ad Data Enter Lock Register 3 AAA AA 555 55 Command (4) Set Lock Register DATA (5) Program Lock Register DATA 1 X (5) ...
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Ad address, Dat data, BAd any address in the block, RD read data, PWDn password byte PWAn password address ( 7), X don’t care. All values in the table are in hexadecimal. 2. ...
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Table 16. Block protection commands, 16-bit mode Command 1st Ad Enter Lock Register 3 555 (4) Command Set Lock Register Program 2 X Lock Register Read 1 X Enter Password Protection Command 3 555 (4) Set (6)(7) Password Program 2 ...
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Table 17. Program, erase times and program, erase endurance cycles Parameter Chip Erase (4) Block Erase (128 kbytes) Erase Suspend latency time Block Erase timeout Single Byte Program Byte Program Write to Buffer Program (64 bytes at-a-time) Single Word Program ...
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... When shipped from the factory, all parts default to operate in non-volatile protection mode. The memory blocks can be either unprotected (NVPBs set to ‘1’) or protected (NVPBs set to ‘0’), according to the ordering option that has been chosen. ...
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Table 18. Lock register bits DQ15-3 DQ2 Password protection mode Don’t care lock bit 1. DQ0, DQ1 and DQ2 lock register bits are set to ‘1’ when shipped from the factory. Table 19. Block protection status Block (1) NVPB lock ...
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Figure 7. Lock register program flowchart Write Lock Register Exit command: Device returned Add Dont' care, Data 90h to Read mode Add Dont' care, Data 00h the programmed data (see Table 18: Lock register 2. The lock ...
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... The error bit can be used to identify errors detected by the program/erase controller. The error bit is set to ’1’ when a program, block erase or chip erase operation fails to write the correct data to the memory. If the error bit is set a Read/Reset command must be issued Table 20: Status register flowchart, gives an example of how to use the data polling bit ...
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... Note that the Program command cannot change a bit set to ’0’ back to ’1’ and attempting will set DQ5 to ‘1’. A bus read operation to that address will show the bit is still ‘0’. One of the erase commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’. ...
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Table 20. Status register bits Operation (2) Program Program during erase suspend (2) Buffered program abort Program error Chip erase Block erase before timeout Block erase Erase suspend Erase error 1. Unspecified data bits should be ignored. DQ7 2. for ...
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Figure 8. Data polling flowchart 56/94 START READ DQ5 & DQ7 at VALID ADDRESS DQ7 YES = DATA NO NO DQ5 = 1 YES READ DQ7 at VALID ADDRESS DQ7 YES = DATA NO FAIL PASS AI07760 ...
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Figure 9. Data toggle flowchart START READ DQ6 at Valid Address READ DQ5 & DQ6 at Valid Address DQ6 NO = TOGGLE YES NO DQ5 = 1 YES READ DQ6 TWICE at Valid Address DQ6 NO = TOGGLE YES FAIL ...
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Maximum ratings Stressing the device above the rating listed in cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. These are stress ratings only and operation of the device ...
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DC and AC parameters This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics tables that follow, are derived from tests performed under the measurement ...
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Figure 11. AC measurement I/O waveform V CCQ 0 V Table 23. Power-up waiting timings Symbol ( High to Chip Enable Low VCHEL CC ( High to Chip Enable Low VCQHEL CCQ t V High to ...
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Table 24. Device capacitance Symbol Parameter C Input capacitance IN C Output capacitance OUT 1. Sampled only, not 100% tested. Table 25. DC characteristics Symbol Parameter (1) I Input leakage current LI I Output leakage current LO Random read I ...
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Figure 13. Random read AC waveforms (8-bit mode) A0-A22 E G DQ0-DQ14, DQ15A-1 Note: BYTE = V IL Figure 14. Random read AC waveforms (16-bit mode) A–1,A0-A22 E G DQ0-DQ7 Note: BYTE = V IH 62/ Vccq +/- ...
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Figure 15. BYTE transition AC waveforms A0-A MAX A–1 BYTE# DQ0-DQ7 DQ8-DQ15 tBLQZ Note: Chip Enable (E) and Output Enable ( VALID VALID tAVQV tBLQX Hi-Z IL tAXQX tBHQV DATA OUT DATA OUT Byte_Transition_AC-Waveform 63/94 ...
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Figure 16. Page read AC waveforms (16-bit mode) 64/94 ...
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Table 26. Read AC characteristics Symbol Alt. Parameter Address Valid to Next t t AVAV RC Address Valid Address Valid to Output t t AVQV ACC Valid Address Valid to Output t t AVQV1 PAGE Valid (page) Chip Enable Low ...
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... Only the third and fourth cycles of the Program command are represented. The Program command is followed by the check of status register data polling bit and by a read operation that outputs the data, DOUT, programmed by the previous Program command the address of the memory location to be programmed the data to be programmed. 3. DQ7 is the complement of the data bit being programmed to DQ7 (see 4. ...
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... Only the third and fourth cycles of the Program command are represented. The Program command is followed by the check of status register data polling bit and by a read operation that outputs the data, DOUT, programmed by the previous Program command the address of the memory location to be programmed the data to be programmed. 3. DQ7 is the complement of the data bit being programmed to DQ7 (see 4. ...
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M Table 27. Write AC characteristics, write enable controlled Symbol Alt t t Address Valid to Next Address Valid AVAV Chip Enable Low to Write Enable Low ELWL Write Enable Low to Write Enable ...
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... Only the third and fourth cycles of the Program command are represented. The Program command is followed by the check of status register data polling bit the address of the memory location to be programmed the data to be programmed. 3. DQ7 is the complement of the data bit being programmed to DQ7 (see 4 ...
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... Only the third and fourth cycles of the Program command are represented. The Program command is followed by the check of status register data polling bit the address of the memory location to be programmed the data to be programmed. 3. DQ7 is the complement of the data bit being programmed to DQ7 (see 4 ...
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Figure 21. Chip/block erase waveforms (8-bit mode) tAVAV A0-A22/ A–1 tELWL E tGHWL G tWLWH W tDVWH DQ0-DQ7 1. For a Chip Erase command, addresses and data are 555h and 10h, respectively, while they are BAd and 30h for a ...
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Figure 22. Reset AC waveforms (no program/erase ongoing tPLPX Figure 23. Reset during program/erase operation AC waveforms tPLPX Table 29. Reset AC characteristics Symbol Alt. t (2) READ t RP ...
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Figure 24. Accelerated program timing waveforms V PPH tVHVPP Figure 25. Data polling AC waveforms tWHEH DQ7 DATA DQ6-DQ0 DATA R/B 1. DQ7 returns valid data bit when the ...
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Figure 26. Toggle/alternative toggle bit polling AC waveforms (8-bit mode) A0-A22/ A–1 E tWHGL2 W G tWHDX DQ6/DQ2 Data tWHRL R/B 1. DQ6 stops toggling when the ongoing Program or Erase command is completed. DQ2 stops toggling when the ongoing ...
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... Package mechanical To meet environmental requirements, Numonyx offers these devices in RoHS compliant packages, which are lead-free. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ...
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Figure 28. TBGA64 active ball array pitch, package outline, bottom view BALL "A1" Drawing is not to scale. Table 32. TBGA64 ...
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Figure 29. FBGA64 mm— active ball array pitch, package outline, bottom view BALL "A1" Drawing is not to scale. Table 33. FBGA64 mm—8 x ...
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... Note: This product is also available with the extended memory block factory locked. For further details and ordering information contact your nearest Numonyx sales office. Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest Numonyx sales office ...
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Appendix A Block addresses and read/modify protection groups Table 35. Block addresses Block Protection group 0 Protection group 1 Protection group 2 Protection group 3 Protection group 4 Protection group 5 Protection group 6 Protection group 7 Protection group 8 ...
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Table 35. Block addresses (continued) Block Protection group 30 Protection group 31 Protection group 32 Protection group 33 Protection group 34 Protection group 35 Protection group 36 Protection group 37 Protection group 38 Protection group 39 Protection group 40 Protection ...
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Table 35. Block addresses (continued) Block Protection group 63 Protection group 64 Protection group 65 Protection group 66 Protection group 67 Protection group 68 Protection group 69 Protection group 70 Protection group 71 Protection group 72 Protection group 73 Protection ...
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Table 35. Block addresses (continued) Block Protection group 96 Protection group 97 Protection group 98 Protection group 99 Protection group 100 Protection group 101 Protection group 102 Protection group 103 Protection group 104 Protection group 105 Protection group 106 Protection ...
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... A0-A7) used to retrieve the data. The CFI data structure also contains a security area where a 64-bit unique security number is written (see accessed only in read mode by the final user impossible to change the security number after it has been written by Numonyx. Table 36. Query structure overview ...
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Table 38. CFI query system interface information Address Data x16 x8 1Bh 36h 0027h 1Ch 38h 0036h 1Dh 3Ah 00B5h 1Eh 3Ch 00C5h 1Fh 3Eh 0004h 20h 40h 0004h 21h 42h 0009h 22h 44h 0010h 23h 46h 0004h 24h 48h ...
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Table 39. Device geometry definition Address Data x16 x8 27h 4Eh 0018h Device size = 2 28h 50h 0002h Flash device interface code description 29h 52h 0000h 2Ah 54h 0006h Maximum number of bytes in multiple-byte program or page= 2 ...
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Table 40. Primary algorithm-specific extended query table Address Data x16 x8 40h 80h 0050h 41h 82h 0052h 42h 84h 0049h 43h 86h 0031h 44h 88h 0033h 45h 8Ah 000Dh 46h 8Ch 0002h 47h 8Eh 0001h 48h 90h 0000h 49h 92h ...
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Table 41. Security code area Address Data x16 x8 61h C3h, C2h XXXX 62h C5h, C4h XXXX 63h C7h, C6h XXXX 64h C9h, C8h XXXX Description 64-bit: unique device number 87/94 ...
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... The device can be shipped either with the extended memory block factory locked, or factory unlocked. If the extended memory block is not factory locked, it can be customer lockable. Its status is indicated by bit DQ7. This bit is permanently set to either ‘1’ or ‘0’ at the factory and cannot be changed. When set to ‘ ...
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... Customer lockable extended memory block A device where the extended memory block is customer lockable is delivered with the DQ7 bit set to ‘0’ and the extended memory block unprotected the customer to program and protect the extended memory block but care must be taken because the protection of the extended memory block is not reversible ...
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Appendix D Flowcharts Figure 30. Write to buffer program flowchart and pseudocode 1. n+1 is the number of addresses to be programmed write to buffer program abort and reset must be issued to return the device in read ...
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Figure 31. Enhanced buffered program flowchart and pseudocode NO NO DQ1 = 1 YES 1. A buffered program abort and reset must be issued to return the device in read mode. 2. When the block address is specified, all the ...
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... Operating and AC measurement 28-Jan-2008 3 Table 40: Primary algorithm-specific extended query Added: Changed erase suspend latency time in program, erase endurance Minor text changes. 20-Mar-2008 4 Applied Numonyx branding. Modified: Table 23: Power-up waiting query 21-Apr-2008 5 Added t Reset AC waveforms (no program/erase program/erase operation AC Minor text changes. 92/94 ...
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Table 43. Document revision history (continued) Date Version Added automotive device grade and automotive qualified information to cover page 6-Oct-2008 6 and order information page. Made the following changes: – New ambient temperature range °C) to ...
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... NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems nuclear facility Numonyx may make changes to specifications and product descriptions at any time, without notice. ...