IC SRAM 9MBIT 80NS 100TQFP

 

IDT71V67703S80PFG8

Manufacturer Part NumberIDT71V67703S80PFG8
DescriptionIC SRAM 9MBIT 80NS 100TQFP
ManufacturerIDT, Integrated Device Technology Inc
IDT71V67703S80PFG8 datasheets

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Specifications of IDT71V67703S80PFG8

Format - MemoryRAMMemory TypeSRAM - Synchronous
Memory Size9M (256K x 36)Speed80ns
InterfaceParallelVoltage - Supply3.135 V ~ 3.465 V
Operating Temperature0°C ~ 70°CPackage / Case100-TQFP, 100-VQFP
Lead Free Status / RoHS StatusLead free / RoHS CompliantOther names71V67703S80PFG8
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256K x 36, 512K x 18 memory configurations
Supports fast access times:
– 7.5ns up to 117MHz clock frequency
– 8.0ns up to 100MHz clock frequency
– 8.5ns up to 87MHz clock frequency
LBO
LBO input selects interleaved or linear burst mode
LBO
LBO
LBO
Self-timed write cycle with global write control (GW
BWE
BWE
BW
BW
BWE
BWE), and byte writes (BW
BWx)
BW
enable (BWE
3.3V core power supply
Power down controlled by ZZ input
3.3V I/O supply (V
)
DDQ
Packaged in a JEDEC Standard 100-pin thin plastic quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball
grid array (fBGA).
The IDT71V67703/7903 are high-speed SRAMs organized as
256K x 36/512K x 18. The IDT71V67703/7903 SRAMs contain write,
A
-A
Address Inputs
0
18
Chip Enable
CS
,
Chip Selects
0
1
Output Enable
Global Write Enable
Byte Write Enable
Individual Byte Write Selects
(1)
,
,
,
1
2
3
4
CLK
Clock
Burst Address Advance
Address Status (Cache Controller)
Address Status (Processor)
Linear / Interleaved Burst Order
ZZ
Sleep Mode
I/O
-I/O
, I/O
-I/O
Data Input / Output
0
31
P1
P4
V
, V
Core Power, I/O Power
DD
DDQ
V
Ground
SS
NOTE:
1. BW
and BW
are not applicable for the IDT71V67903.
3
4
©2002 Integrated Device Technology, Inc.
256K X 36, 512K X 18
3.3V Synchronous SRAMs
3.3V I/O, Burst Counter
Flow-Through Outputs, Single Cycle Deselect
data, address and control registers. There are no registers in the data
output path (flow-through architecture). Internal logic allows the SRAM to
generate a self-timed write based upon a decision which can be left until
the end of the write cycle.
The burst mode feature offers the highest level of performance to the
system designer, as the IDT71V67703/7903 can provide four cycles of
data for a single address presented to the SRAM. An internal burst address
GW
GW
GW
GW), byte write
counter accepts the first cycle address from the processor, initiating the
access sequence. The first cycle of output data will flow-through from the
array after a clock-to-data access time delay from the rising clock edge of
the same cycle. If burst mode operation is selected (ADV=LOW), the
subsequent three cycles of output data will be available to the user on the
next three rising clock edges. The order of these three addresses are
defined by the internal burst counter and the LBO input pin.
The IDT71V67703/7903 SRAMs utilize IDT’s latest high-performance
CMOS process and are packaged in a JEDEC standard 14mm x 20mm
100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array
(BGA) and a 165 fine pitch ball grid array (fBGA).
1
IDT71V67703
IDT71V67903
Input
Synchronous
Input
Synchronous
Input
Synchronous
Input
Asynchronous
Input
Synchronous
Input
Synchronous
Input
Synchronous
Input
N/A
Input
Synchronous
Input
Synchronous
Input
Synchronous
Input
DC
Input
Asynchronous
I/O
Synchronous
Supply
N/A
Supply
N/A
5309 tbl 01
FEBRUARY 2009
DSC-5309/05

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IDT71V67703S80PFG8 Summary of contents

  • Page 1

    ... Supports fast access times: – 7.5ns up to 117MHz clock frequency – 8.0ns up to 100MHz clock frequency – 8.5ns up to 87MHz clock frequency LBO LBO input selects interleaved or linear burst mode LBO LBO LBO Self-timed write cycle with global write control (GW ...

  • Page 2

    IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Symbol Pin Function I Address Inputs Address Status I (Cache Controller) Address Status I (Processor) Burst ...

  • Page 3

    ... Write Register Byte 2 Write Register Byte 3 Write Register Byte 4 Write Register Q D Enable Register CLK EN 6.42 3 INTERNAL ADDRESS 256K x 36/ 18/19 512K x 18- BIT A0* MEMORY A1* ARRAY 36/18 Byte 1 Write Driver 9 Byte 2 Write Driver 9 Byte 3 Write Driver 9 Byte 4 Write Driver 9 DATA INPUT REGISTER ...

  • Page 4

    IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Symbol Rating (2) V Terminal Voltage with TERM Respect to GND (3,6) V Terminal Voltage with TERM Respect to GND (4,6) ...

  • Page 5

    IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect DDQ I ...

  • Page 6

    IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect 100 DDQ V ...

  • Page 7

    IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect DDQ I I DDQ G I ...

  • Page 8

    IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect I/O I ...

  • Page 9

    IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Symbol Parameter |I | Input Leakage Current LI ( Input Leakage Current Output Leakage Current LO ...

  • Page 10

    IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Operation Address Used Deselected Cycle, Power Down None Deselected Cycle, Power Down None Deselected Cycle, Power Down None Deselected Cycle, Power ...

  • Page 11

    IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Operation Read Read Write all Bytes Write all Bytes (3) Write Byte 1 (3) Write Byte 2 (3) Write Byte 3 ...

  • Page 12

    IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Symbol Clock Parameter t Clock Cycle Time CYC (1) Clock High Pulse Width t CH (1) Clock Low Pulse Width t ...

  • Page 13

    IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges , 6.42 13 ...

  • Page 14

    IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges 6. ...

  • Page 15

    IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges GW 6. ...

  • Page 16

    IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges 6. ...

  • Page 17

    IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges , 6.42 17 ...

  • Page 18

    IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect CLK ADDRESS CE DATA ...

  • Page 19

    IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges 6.42 19 ...

  • Page 20

    IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges 6.42 20 ...

  • Page 21

    IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges 6.42 21 ...

  • Page 22

    IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect XXX S X Device Power Speed Package Type XX X Process/ Temperature Rance Commercial (0°C to +70°C) Blank Industrial (-40°C to ...

  • Page 23

    IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect 12/31/99 Created Datasheet from 71V677 and 71V679 Datasheets For 2.5V I/O offering, see 71V67702 AND 71V67902 Datasheets. 04/26/00 Pg. 4 Add ...

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