IC FLASH 2MBIT 90NS 52PLCC

 

PSD834F2-90J

Manufacturer Part NumberPSD834F2-90J
DescriptionIC FLASH 2MBIT 90NS 52PLCC
ManufacturerSTMicroelectronics
PSD834F2-90J datasheets

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Specifications of PSD834F2-90J

Format - MemoryFLASHMemory TypeFLASH
Memory Size2M (256K x 8)Speed90ns
InterfaceParallelVoltage - Supply4.5 V ~ 5.5 V
Operating Temperature0°C ~ 70°CPackage / Case52-PLCC
Lead Free Status / RoHS StatusContains lead / RoHS non-compliantOther names497-2006-5
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Download datasheet (909Kb)Embed
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Table 57. WRITE Timing (5V devices)
Symbol
Parameter
t
ALE or AS Pulse Width
LVLX
t
Address Setup Time
AVLX
t
Address Hold Time
LXAX
Address Valid to Leading
t
AVWL
Edge of WR
t
CS Valid to Leading Edge of WR
SLWL
t
WR Data Setup Time
DVWH
t
WR Data Hold Time
WHDX
t
WR Pulse Width
WLWH
t
Trailing Edge of WR to Address Invalid
WHAX1
Trailing Edge of WR to DPLD Address
t
WHAX2
Invalid
Trailing Edge of WR to Port Output
t
WHPV
Valid Using I/O Port Data Register
Data Valid to Port Output Valid
t
Using Macrocell Register
DVMV
Preset/Clear
Address Input Valid to Address
t
AVPV
Output Delay
WR Valid to Port Output Valid Using
t
WLMV
Macrocell Register Preset/Clear
Note: 1. Any input used to select an internal PSD function.
2. In multiplexed mode, latched address generated from ADIO delay to address output on any port.
3. WR has the same timing as E, LDS, UDS, WRL, and WRH signals.
4. Assuming data is stable before active WRITE signal.
5. Assuming WRITE is active before data becomes valid.
6. TWHAX2 is the address hold time for DPLD inputs that are used to generate Sector Select signals for internal PSD memory.
-70
Conditions
Min Max Min Max Min Max
15
1
4
(Note
)
1
7
(Note
)
1,3
8
(Notes
)
3
12
(Note
)
3
25
(Note
)
3
4
(Note
)
3
31
(Note
)
3
6
(Note
)
3,6
0
(Note
)
3
(Note
)
3,5
(Notes
)
2
(Note
)
3,4
(Notes
)
Doc ID 10552 Rev 3
PSD813F2V, PSD854F2V
-90
-15
Unit
20
28
ns
6
10
ns
8
11
ns
15
20
ns
15
20
ns
35
45
ns
5
5
ns
35
45
ns
8
10
ns
0
0
ns
27
30
38
ns
42
55
65
ns
20
25
30
ns
48
55
65
ns
91/109