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PSD834F2-90J
PSD834F2-90J | |
|---|---|
| Manufacturer Part Number | PSD834F2-90J |
| Description | IC FLASH 2MBIT 90NS 52PLCC |
| Manufacturer | STMicroelectronics |
| PSD834F2-90J datasheets |
|
Availability: In stock
International delivery:
Warranty: 60 days
×
- We provide standard 60-days warranty for all parts. If warranty differs we always mention it beforehand. In case of return we cover shipping costs.
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Specifications of PSD834F2-90J | |||
|---|---|---|---|
| Format - Memory | FLASH | Memory Type | FLASH |
| Memory Size | 2M (256K x 8) | Speed | 90ns |
| Interface | Parallel | Voltage - Supply | 4.5 V ~ 5.5 V |
| Operating Temperature | 0°C ~ 70°C | Package / Case | 52-PLCC |
| Lead Free Status / RoHS Status | Contains lead / RoHS non-compliant | Other names | 497-2006-5 |
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PSD813F2V, PSD854F2V
Table 64. Port A Peripheral Data Mode WRITE Timing (3V devices)
Symbol
Parameter
t
WR to Data Propagation Delay
WLQV–PA
t
Data to Port A Data Propagation Delay
DVQV–PA
t
WR Invalid to Port A Tri-state
WHQZ–PA
Note: 1. RD has the same timing as DS, LDS, UDS, and PSEN (in 8031 combined mode).
2. WR has the same timing as the E, LDS, UDS, WRL, and WRH signals.
3. Any input used to select Port A Data Peripheral mode.
4. Data is already stable on Port A.
5. Data stable on ADIO pins to data on Port A.
Figure 49. Reset (RESET) Timing
V
(min)
V
CC
CC
t NLNH-PO
Power-On Reset
RESET
Table 65. Reset (RESET) Timing (5V devices)
Symbol
Parameter
t
RESET Active Low Time
NLNH
t
Power On Reset Active Low Time
NLNH–PO
t
Warm Reset (on the PSD834Fx)
NLNH–A
t
RESET High to Operational Device
OPR
Note: 1. Reset (RESET) does not reset Flash memory Program or Erase cycles.
2. Warm reset aborts Flash memory Program or Erase cycles, and puts the device in READ Mode.
Table 66. Reset (RESET) Timing (3V devices)
Symbol
Parameter
t
RESET Active Low Time
NLNH
t
Power On Reset Active Low Time
NLNH–PO
t
Warm Reset (on the PSD834Fx)
NLNH–A
t
RESET High to Operational Device
OPR
Note: 1. Reset (RESET) does not reset Flash memory Program or Erase cycles.
2. Warm reset aborts Flash memory Program or Erase cycles, and puts the device in READ Mode.
96/109
Conditions
Min Max Min Max Min Max
2
(Note
)
5
(Note
)
2
(Note
)
t OPR
Conditions
1
2
Conditions
1
2
Doc ID 10552 Rev 3
-12
-15
-20
42
45
55
38
40
45
33
33
35
t NLNH
t NLNH-A
t OPR
Warm Reset
AI02866b
Min
Max
150
1
25
120
Min
Max
300
1
25
300
Unit
ns
ns
ns
Unit
ns
ms
μs
ns
Unit
ns
ms
μs
ns
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