LH28F160BJHE-TTL90 Sharp Microelectronics, LH28F160BJHE-TTL90 Datasheet
LH28F160BJHE-TTL90
Specifications of LH28F160BJHE-TTL90
LH28F160BJHE-BTL90
LHF16J04
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LH28F160BJHE-TTL90 Summary of contents
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... P S RODUCT PECIFICATIONS LH28F160BJHE-TTL90 Flash Memory 16M (1MB × 2MB × 8) Issue Date: February 14, 2003 ® (Model No.: LHF16J04) Spec No.: EL152050 Integrated Circuits Group ...
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Any reproduction, full or in part, of this material is prohibited without the express written permission of the company. ●When using the products covered herein, please ...
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INTRODUCTION.............................................................. 3 1.1 Features ........................................................................ 3 1.2 Product Overview......................................................... 3 1.3 Product Description...................................................... 4 1.3.1 Package Pinout ....................................................... 4 1.3.2 Block Organization................................................. 4 2 PRINCIPLES OF OPERATION........................................ 7 2.1 Data Protection............................................................. 8 3 BUS OPERATION ............................................................ 8 3.1 ...
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... Top Boot Location ■ Extended Cycling Capability Minimum 100,000 Block Erase Cycles SHARP’s LH28F160BJHE-TTL90 Flash memory is a high-density, low-cost, nonvolatile, read/write storage solution for a wide range of applications. LH28F160BJHE-TTL90 can operate at V capability realize battery life and suits for cellular phone application. ...
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... V off during read operation. CCW 1.2 Product Overview The LH28F160BJHE-TTL90 is a high-performance 16M- bit Boot Block Flash memory organized as 1M-word of 16 bits or 2M-byte of 8 bits. The 1M-word/2M-byte of data is arranged in two 4K-word/8K-byte boot blocks, six 4K- word/8K-byte parameter blocks and thirty-one 32K- word/64K-byte main blocks which are individually erasable, lockable and unlockable in-system ...
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... For example, changing data from "10111101" to "10111100" requires "11111110" programming. LHF16J04 1.3 Product Description supply CC 1.3.1 Package Pinout LH28F160BJHE-TTL90 Boot Block Flash memory is available in 48-lead TSOP package (see Figure 2). CCR 1.3.2 Block Organization , the I CMOS CC This product architecture providing system memory integration ...
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Input A -A Decoder -1 19 Buffer Address Decoder Latch Address Counter ...
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... Boot and Parameter Block Address DATA INPUT/OUTPUTS: Inputs data and commands during CUI write cycles; outputs data during memory array, status register and identifier code read cycles. Data pins float to high- INPUT/ DQ -DQ impedance when the chip is deselected or outputs are disabled. Data is internally latched during a ...
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... PRINCIPLES OF OPERATION The LH28F160BJHE-TTL90 flash memory includes an on-chip WSM to manage block erase, full chip erase, word/byte write and lock-bit configuration functions. It allows for: 100% TTL-level control inputs, fixed power supplies during block erase, full chip erase, word/byte write and lock-bit configuration, and minimal processor overhead with RAM-like interface timings ...
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... Refer to Table 5 for write protection alternatives. 3 BUS OPERATION The local CPU reads and writes flash memory in-system. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles. 3.1 Read Information can be read from any block, identifier codes ...
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... Lock locked. The Clear Block Lock-Bits command requires the command and address within the device. The CUI does not occupy an addressable memory location written when WE# and CE# are active. The address and data needed to execute a command are latched on the rising edge of WE# or CE# (whichever goes high first) ...
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... IH IL Table 2.2. Bus Operations (BYTE#=V RP# CE# OE# WE ≤V , memory contents can be read, but not altered. CCW CCWLK or V CCWLK CCWH1/2 (1,2) ) Address V DQ RY/BY# CCW 0- OUT X X High High High Z High Z See X Note 5 High Z Figure (1, Address V DQ RY/BY# CCW 0 OUT X ...
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... IA=Identifier Code Address: see Figure 4. BA=Address within the block being erased. WA=Address of memory location to be written. 3. SRD=Data read from status register. See Table 6 for a description of the status register bits. WD=Data to be written at location WA. Data is latched on the rising edge of WE# or CE# (whichever goes high first). ...
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... Future Use Permanent Lock Configuration 00003H •Device is Unlocked •Device is Locked •Reserved for Future Use NOTE selects the specific block lock configuration code to be read. See Figure 4 for the device identifier code memory map don’t care in byte mode -DQ outputs 00H in word mode LHF16J04 4 ...
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... The CUI remains in read status register mode until it receives another command. Reliable word/byte writes can only occur when V =2.7V-3.6V and V CC this high voltage, memory contents are protected against word/byte writes. If word/byte write is attempted while ≤V V CCW CCWLK set to "1". Successful word/byte write requires for boot blocks that WP bit be cleared ...
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... The only other valid commands while block erase is suspended are Read Status Register and Block Erase Resume. After a Block Erase Resume command is written to the flash memory, the WSM will continue the block erase process. Status register bits SR.6 and SR.7 will automatically clear and RY/BY# will return to V ...
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Set Block and Permanent Lock-Bit Commands A flexible block locking and unlocking scheme is enabled via a combination of block lock-bits, a permanent lock-bit and WP# pin. The block lock-bits and WP# pin gates program and erase operations ...
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... Block Locking by the WP# This Boot Block Flash memory architecture features two hardware-lockable boot blocks so that the kernel code for the system can be kept secure while other blocks are programmed or erased as necessary. The lockable two boot blocks are locked when WP#=V ...
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WSMS BESS ECBLBS SR.7 = WRITE STATE MACHINE STATUS (WSMS Ready 0 = Busy SR.6 = BLOCK ERASE SUSPEND STATUS (BESS Block Erase Suspended 0 = Block Erase in Progress/Completed SR.5 = ...
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Start Write 70H Read Status Register 0 SR.7= 1 Write 20H Write D0H, Block Address Read Status Register No 0 Suspend SR.7= Block Erase 1 Full Status Check if Desired Block Erase Complete FULL STATUS CHECK PROCEDURE Read Status ...
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Start Write 70H Read Status Register 0 SR.7= 1 Write 30H Write D0H Read Status Register 0 SR.7= 1 Full Status Check if Desired Full Chip Erase Complete FULL STATUS CHECK PROCEDURE Read Status Register Data(See Above ...
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Start Write 70H Read Status Register 0 SR.7= 1 Write 40H or 10H Write Word/Byte Data and Address Read Status Register No Suspend 0 SR.7= Word/Byte Write 1 Full Status Check if Desired Word/Byte Write Complete FULL STATUS CHECK ...
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Start Write B0H Read Status Register 0 SR. SR.6= Block Erase Completed 1 Read or Word/Byte Write Read Word/Byte Write ? Read Array Data Word/Byte Write Loop No Done? Yes Write D0H Block Erase Resumed Figure 8. ...
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Start Write B0H Read Status Register 0 SR. Word/Byte Write Completed SR.2= 1 Write FFH Read Array Data Done No Reading Yes Write D0H Write FFH Word/Byte Write Resumed Read Array Data Figure 9. Word/Byte Write Suspend/Resume ...
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Start Write 70H Read Status Register 0 SR.7= 1 Write 60H Write 01H/F1H, Block/Device Address Read Status Register 0 SR.7= 1 Full Status Check if Desired Set Lock-Bit Complete FULL STATUS CHECK PROCEDURE Read Status Register Data(See Above) 1 ...
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Start Write 70H Read Status Register 0 SR.7= 1 Write 60H Write D0H Read Status Register 0 SR.7= 1 Full Status Check if Desired Clear Block Lock-Bits Complete FULL STATUS CHECK PROCEDURE Read Status Register Data(See Above) 1 SR.3= ...
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... DESIGN CONSIDERATIONS 5.1 Three-Line Output Control The device will often be used in large memory arrays. SHARP provides three control inputs to accommodate multiple memory connections. Three-line control provides for: a. Lowest possible memory power dissipation. b. Complete assurance that data bus contention will not occur ...
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... By setting a WP# to low, only the 2 boot blocks can be protected against overwriting. By using this feature, the flash memory space can be divided into the program section (locked section) and data section (unlocked section). The permanent lock bit can be used to prevent false block bit setting ...
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ELECTRICAL SPECIFICATIONS 6.1 Absolute Maximum Ratings* Operating Temperature During Read, Block Erase, Full Chip Erase, Word/Byte Write and Lock-Bit Configuration .............-40°C to +85°C Storage Temperature During under Bias ............................... -40°C to +85°C During non Bias ................................ -65°C to ...
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AC INPUT/OUTPUT TEST CONDITIONS 2.7 INPUT 0.0 AC test inputs are driven at 2.7V for a Logic "1" and 0.0V for a Logic "0". Input timing begins, and output timing ends, at 1.35V. Input rise and fall times ...
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DC CHARACTERISTICS Sym. Parameter I Input Load Current LI I Output Leakage Current Standby Current CCS Auto Power-Save Current CCAS Reset Power-Down Current CCD Read Current ...
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Sym. Parameter V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage OH1 (TTL) V Output High Voltage OH2 (CMOS Lockout during Normal CCWLK CCW Operations V V ...
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AC CHARACTERISTICS - READ-ONLY OPERATIONS Sym. Parameter t Read Cycle Time AVAV t Address to Output Delay AVQV t CE# to Output Delay ELQV t RP# High to Output Delay PHQV t OE# to Output Delay GLQV t ...
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Standby Address Selection V IH ADDRESSES( CE#( OE#( WE#( HIGH Z DATA(D/Q) (DQ - PHQV ...
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Standby Address Selection V IH ADDRESSES( CE#( OE#( BYTE#( HIGH Z DATA(D/Q) (DQ - HIGH Z ...
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AC CHARACTERISTICS - WRITE OPERATIONS Sym. Parameter t Write Cycle Time AVAV t RP# High Recovery to WE# Going Low PHWL t CE# Setup to WE# Going Low ELWL t WE# Pulse Width WLWH t WP#V Setup to ...
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V IH ADDRESSES( CE#( OE#( WE#( DATA(D/ BYTE#( High Z ("1") RY/BY#(R) (SR. ("0") ...
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ALTERNATIVE CE#-CONTROLLED WRITES Sym. Parameter t Write Cycle Time AVAV t RP# High Recovery to CE# Going Low PHEL t WE# Setup to CE# Going Low WLEL t CE# Pulse Width ELEH t WP#V Setup to CE# Going ...
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V IH ADDRESSES( CE#( OE#( WE#( DATA(D/ BYTE#( High Z ("1") RY/BY#(R) (SR. ("0") V ...
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RESET OPERATIONS High Z ("1") RY/BY#(R) (SR. ("0" RP#( High Z ("1") RY/BY#(R) (SR. ("0" RP#( (B)Reset During Block Erase, Full Chip Erase, Word/Byte Write or ...
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BLOCK ERASE, FULL CHIP ERASE, WORD/BYTE WRITE AND LOCK-BIT CONFIGURATION PERFORMANCE Sym. Parameter t Word Write Time 32K word Block WHQV1 t 4K word Block EHQV1 Byte Write Time 64K byte Block 8K byte Block Block Write Time ...
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A-1 RECOMMENDED OPERATING CONDITIONS A-1.1 At Device Power-Up AC timing illustrated in Figure A-1 is recommended for the supply voltages and the control signals at device power-up. If the timing in the figure is ignored, the device may not ...
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A-1.1.1 Rise and Fall Time Symbol t V Rise Time Input Signal Rise Time R t Input Signal Fall Time F NOTES: 1. Sampled, not 100% tested. 2. This specification is applied for not only the ...
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A-1.2 Glitch Noises Do not input the glitch noises which are below V as shown in Figure A-2 (b). The acceptable glitch noises are illustrated in Figure A-2 (a). Input Signal V (Min (Max.) IL Input Signal ...
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... A-2 RELATED DOCUMENT INFORMATION Document No. AP-001-SD-E Flash Memory Family Software Drivers AP-006-PT-E Data Protection Method of SHARP Flash Memory RP#, V AP-007-SW-E NOTE: 1. International customers should contact their local SHARP or distribution sales office. (1) Document Name Electric Potential Switching Circuit PP iv Rev. 1.10 ...
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... ALL EXPRESS AND IMPLIED WARRANTIES, INCLUDING THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR USE AND FITNESS FOR A PARTICULAR PURPOSE, ARE SPECIFICALLY EXCLUDED event will SHARP be liable any way responsible, for any incidental or consequential economic or property damage. NORTH AMERICA SHARP Microelectronics of the Americas 5700 NW Pacific Rim Blvd. Camas, WA 98607, U.S.A. Phone: (1) 360-834-2500 ...