PSD4235G2-90UI STMicroelectronics, PSD4235G2-90UI Datasheet
PSD4235G2-90UI
Specifications of PSD4235G2-90UI
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PSD4235G2-90UI Summary of contents
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... Erase/write c ycles of Flash memory – 1,000 Erase/WRITE Cycles of PLD – 15 Year Data Retention ■ Single supply voltage – 5V ±10% ■ Memory speed – 70ns Flash memory and SRAM access time ■ Packages are ECOPACK Rev 4 PSD4235G2 ® 1/129 www.st.com 1 ...
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... Register bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.1 Data-In registers - port 6.2 Data-out registers - port 6.3 Direction registers - ports 6.4 Control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2/129 First time programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Inventory build-up of pre-programmed devices . . . . . . . . . . . . . . . . . . . 12 Expensive sockets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Simultaneous READ and WRITE to Flash memory . . . . . . . . . . . . . . . . 13 Complex memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Separate Program and Data space . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 PSD4235G2 ...
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... PSD4235G2 6.5 Drive registers - Ports 6.6 Drive registers - Ports C and 6.7 Enable-Out registers - Ports 6.8 Input macrocells registers- ports 6.9 Output macrocells A/B registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.10 Mask macrocells A/B registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.11 Flash Memory Protection register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.12 Flash Boot Protection register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.13 JTAG Enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6 ...
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... Program and Data spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 13.3 Separate space modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 13.4 Combined space modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 13.5 80C51XA memory map example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 14 Page register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 15 Memory ID registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 16 PLDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 17 Decode PLD (DPLD Complex PLD (CPLD 18.1 Output macrocell (OMC 18.2 Product Term Allocator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4/129 PSD4235G2 ...
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... PSD4235G2 18.3 Loading and Reading the output macrocells (OMC 18.4 The OMC Mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 18.5 The output Enable of the OMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 18.6 Input macrocells (IMC 18.7 External Chip Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 19 MCU bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 19.1 PSD interface to a multiplexed bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 19.2 PSD interface to a non-multiplexed 8-bit bus . . . . . . . . . . . . . . . . . . . . . . 71 19 ...
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... Reset of Flash Memory Erase and Program cycles . . . . . . . . . . . . . . . . . 99 23 Programming in-circuit using the JTAG serial interface . . . . . . . . . . 101 23.1 Standard JTAG signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 23.2 JTAG extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 23.3 Security and Flash memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . 102 24 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 25 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 6/129 PSD4235G2 ...
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... PSD4235G2 26 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 27 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 28 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Appendix A Pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 29 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Contents 7/129 ...
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... Port Configuration registers (PCR Table 43. Port Pin Direction Control, output Enable P.T. not defined Table 44. Port Pin Direction Control, output Enable P.T. defined Table 45. Port direction assignment example Table 46. Drive register pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Table 47. Port Data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Table 48. Effect of Power-down mode on ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 8/129 PSD4235G2 ...
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... Table 73. ISC timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Table 74. LQFP80 - 80-lead plastic thin, quad, flat package mechanical data 124 Table 75. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Table 76. PSD4235G2 LQFP80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Table 77. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 = 5.0V (with Turbo mode on 107 CC = 5.0V (with Turbo mode off 108 CC List of tables ...
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... Asynchronous clock mode timing (product term clock 115 Figure 42. Input macrocell timing (product term clock 115 Figure 43. Peripheral I/O write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Figure 44. READ timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Figure 45. WRITE timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Figure 46. Peripheral I/O read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Figure 47. Reset (RESET) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Figure 48. ISC timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 10/129 PSD4235G2 ...
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... PSD4235G2 Figure 49. LQFP80 - 80-lead plastic thin, quad, flat package outline . . . . . . . . . . . . . . . . . . . . . . . . 124 List of figures 11/129 ...
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... Two independent Flash memory arrays are included so that the MCU can execute code from one while erasing and programming the other. Robust product firmware updates in the filed are possible over any communication channel (CAN, Ethernet, UART, J1850, etc) using this unique architecture. Designers are relieved of these problems: 12/129 PSD4235G2 ...
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... PSD4235G2 1.2.1 Simultaneous READ and WRITE to Flash memory How can the MCU program the same memory from which it executing code? It cannot. The PSD allows the MCU to operate the two Flash memory blocks concurrently, reading code from one while erasing and programming the other during IAP. ...
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... Table 1. Pin names PA0-PA7 PB0-PB7 PC0-PC7 PD0-PD3 PE0-PE7 PF0-PF7 PG0-PG7 AD0-AD15 CNTL0-CNTL2 RESET 14/129 CNTL0- CNTL2 PSD4xxxGx 16 AD0-AD15 RESET V SS Pin Port-A Port-B Port-C Port-D Port-E Port-F Port-G Address/Data Control Reset PSD4235G2 8 PA0-PA7 8 PB0-PB7 8 PC0-PC7 4 PD0-PD3 8 PE0-PE7 8 PF0-PF7 8 PG0-PG7 AI04916 Description ...
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... PSD4235G2 Table 1. Pin names (continued Figure 2. LQFP connections PD2 1 PD3 2 AD0 3 AD1 4 AD2 5 AD3 6 AD4 7 GND AD5 10 AD6 11 AD7 12 AD8 13 AD9 14 AD10 15 AD11 16 AD12 17 AD13 18 AD14 19 AD15 20 Pin Supply voltage Ground Summary description Description 60 CNTL1 59 CNTL0 58 PA7 57 PA6 56 PA5 55 PA4 54 PA3 ...
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... The following control signals can be connected to this pin, based on your MCU active low, Read Strobe input clock input. CNTL1 active low, Data Strobe input. 4. LDS - active low, Strobe for low data byte. This pin is connected to the PLDs. Therefore, these signals can be used in decode and other logic equations. 16/129 Description PSD4235G2 ...
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... PSD4235G2 Table 2. Pin description (for the LQFP package) (continued) Pin name Pin Type READ or other Control input pin, with multiple configurations. Depending on the MCU interface selected, this pin can be: 1. PSEN - Program Select Enable, active low in code fetch bus cycle (80C51XA mode) ...
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... Open 3. TERR active low output for the JTAG Serial Interface. Drain I/O PE6 pin of Port E. This port pin can be configured to have the following functions: CMOS PE6 77 1. MCU I/O - standard output or input port. or Open 2. Latched address output. Drain 18/129 Description PSD4235G2 ...
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... PSD4235G2 Table 2. Pin description (for the LQFP package) (continued) Pin name Pin Type I/O PE7 pin of Port E. This port pin can be configured to have the following functions: CMOS PE7 78 1. MCU I/O - standard output or input port. or Open 2. Latched address output. Drain These pins make up Port F. These port pins are configurable and can have the following functions: 1 ...
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... Pin description Figure 3. PSD block diagram 1. Additional address lines can be brought in to the device via Port 20/129 PSD4235G2 AI04990b ...
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... PSD4235G2 3 PSD architectural overview PSD devices contain several major functional blocks. PSD device family. The functions of each block are described briefly in the following sections. Many of the blocks perform multiple functions and are user configurable. 3.1 Memory Each of the memory blocks is briefly discussed in the following paragraphs. A more detailed discussion can be found in The 4 Mbit primary Flash memory is the main memory of the PSD ...
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... Table 4 Name Inputs 82 82 TMS TCK TDI TDO TSTAT TERR Table 5 indicates which programming methods can program PSD4235G2 indicates the JTAG pin assignments. Outputs Product Terms 150 JTAG signal ...
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... PSD4235G2 peripherals, or internal memory and I/O. The Page register can also be used to change the address mapping of the Flash memory blocks into different memory spaces for IAP. 3.9 Power management unit (PMU) The power management unit (PMU) gives the user control of the power consumption on selected functional blocks based on system requirements ...
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... PSDsoft Express directly supports two low cost device programmers form ST: PSDpro and FlashLINK (JTAG). Both of these programmers may be purchased through your local distributor/representative, or directly from our web site using a credit card. The PSD is also supported by thid party device programmers. See our web site for the current list. 24/129 PSD4235G2 Figure 4. ...
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... PSD4235G2 Figure 4. PSDsoft Express development tool Choose MCU and PSD Automatically configures MCU bus interface and other Define PSD Pin and Point and click definition of PSD pin functions, internal nodes, and MCU system memory map Define General Purpose Point and click definition of combin- atorial and registered logic in CPLD ...
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... Read only - Primary Flash Sector C0 Protection Read only - PSD Security and C2 Secondary Flash memory Sector Protection C7 Enables JTAG Port B0 Power Management register 0 B4 Power Management register 2 E0 Page register Places PSD memory areas in E2 Program and/or Data space on an individual basis. PSD4235G2 ...
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... PSD4235G2 Table 6. Register address offset (continued) Port Port Port Register name A B Memory_ID0 Memory_ID1 1. Other registers that are not part of the I/O ports. PSD register description and address offsets Port Port Port Port (1) Other Description Read only - SRAM and Primary F0 memory size ...
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... Port pin 4 Port pin 3 Bit 5 Bit 4 Bit 3 Port pin 5 Port pin 4 Port pin 3 Bit 5 Bit 4 Bit 3 Port pin 5 Port pin 4 Port pin 3 PSD4235G2 Bit 2 Bit 1 Bit 0 Port pin 2 Port pin 1 Port pin 0 Bit 2 Bit 1 Bit 0 Port pin 2 Port pin 1 Port pin 0 Bit 2 ...
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... PSD4235G2 6.5 Drive registers - Ports Table 11. Drive registers - Ports Bit 7 Bit 6 Port pin 7 Port pin 6 Port pin <i>: 0: Port pin <i> is configured for CMOS output driver (default). 1: Port pin <i> is configured for Open Drain output driver. 6.6 Drive registers - Ports C and F Table 12 ...
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... Bit 4 Bit 3 Mcellb 5 Mcellb 4 Mcellb 3 Bit 5 Bit 4 Bit 3 Mcella 5 Mcella 4 Mcella 3 Bit 5 Bit 4 Bit 3 Mcellb 5 Mcellb 4 Mcellb 3 Bit 5 Bit 4 Bit 3 PSD4235G2 Bit 2 Bit 1 Bit 0 Mcella 2 Mcella 1 Mcella 0 Bit 2 Bit 1 Bit 0 Mcellb 2 Mcellb 1 Mcellb 0 Bit 2 Bit 1 Bit 0 Mcella 2 Mcella 1 Mcella 0 Bit 2 Bit 1 ...
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... PSD4235G2 6.12 Flash Boot Protection register Table 20. Flash Boot Protection register Bit 7 Bit 6 Security_ not used Bit Sec<i>_Prot: 1: Secondary Flash memory Sector <i> is write protected. 0: Secondary Flash memory Sector <i> is not write protected. Security_Bit: 0: Security bit in device has not been set. ...
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... ALE input to the PLD AND array is disconnected, saving power. 32/129 Bit 5 Bit 4 Bit 3 PLD PLD Array PLD Array CNTL2 CNTL1 Array ALE Table 34 for the signals that are blocked on pins CNTL0-CNTL2. PSD4235G2 Bit 2 Bit 1 Bit 0 not used PLD PLD Array CNTL0 (set to ’0’) Array Addr ...
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... PSD4235G2 PLD Array WRH 0: WRH/DBE input to the PLD AND array is connected. 1: WRH/DBE input to the PLD AND array is disconnected, saving power. 6.17 VM register Table 25. VM register Bit 7 Bit 6 not used Peripheral mode (set to ’0’) On reset, bit1-Bit4 are loaded to configurations that are selected by the user in PSDsoft Express ...
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... Secondary NVM size is 256 Kbit 3h = Secondary NVM size is 512 Kbit B_type[1: Secondary NVM is Flash memory 1h = Secondary NVM is EEPROM 34/129 Bit 5 Bit 4 Bit 3 S_size 1 S_size 0 F_size 3 Bit 5 Bit 4 Bit 3 B_type 1 B_type 0 B_size 3 PSD4235G2 Bit 2 Bit 1 Bit 0 F_size 2 F_size 1 F_size 0 Bit 2 Bit 1 Bit 0 B_size 2 B_size 1 B_size 0 ...
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... PSD4235G2 7 Detailed operation As shown in Figure ● Memory blocks ● PLD blocks ● MCU bus Interface ● I/O ports ● Power management unit (PMU) ● JTAG-ISP interface The functions of each block are described in the following sections. Many of the blocks perform multiple functions, and are user configurable. ...
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... Program instruction, then test the status of the Programming event. This status test is achieved by a READ operation or polling Ready/Busy (PE4). Flash memory can also be read by using special instructions to retrieve particular Flash device information (sector protect status and ID). 36/129 PSD4235G2 Section 16: ...
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... PSD4235G2 (1)(2)(3) Table 29. Instructions FS0-FS7 or (4) Instruction CSBOOT0- CSBOOT3 (6) READ 1 (7) Read Main Flash ID 1 Read Sector (7)(8) Protection 1 (9) Program a Flash 1 (9) Word Flash Sector 1 (10)(9) Erase (9) Flash Bulk Erase 1 Suspend Sector 1 (11) Erase Resume Sector 1 (12) Erase (7) Reset 1 Unlock Bypass ...
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... The Resume Sector Erase instruction is valid only during the Suspend Sector Erase mode. 13. The Unlock Bypass instruction is required prior to the Unlock Bypass Program instruction. 14. The Unlock Bypass Reset Flash instruction is required to return to reading memory data when the device is in the Unlock Bypass mode. 38/129 PSD4235G2 ...
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... PSD4235G2 8 Instructions An instruction consists of a sequence of specific operations. Each received byte is sequentially decoded by the PSD and not executed as a standard WRITE operation. The instruction is executed when the correct number of bytes are properly received and the time between two consecutive bytes is shorter than the timeout period. Some instructions are structured to include READ operations after the initial WRITE operations ...
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... Erase or Program instruction is being executed by the embedded algorithm. See Section 9: Programming Flash 40/129 Table Table Section 11.1: Flash Memory Sector Table 30. The status byte resides in an memory, for details. PSD4235G2 29). The MCU can read the 29). The identifier for the Table 29). The Protect, for register ...
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... PSD4235G2 Table 30. Status bits DQ7 DQ6 Data Toggle Polling Flag Table 31. Status bits for Motorola DQ15 DQ14 Data Toggle Polling Flag Not guaranteed value, can be read either DQ15-DQ0 represent the Data Bus bits, D15-D0. 3. FS0-FS7/CSBOOT0-CSBOOT3 are active high. 8.7 Data Polling (DQ7) - DQ15 for Motorola When erasing or programming in Flash memory, the Data Polling bit (DQ7/DQ15) outputs the complement of the bit being entered for programming/writing on the DQ7/DQ15 bit ...
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... Sector Erase instructions. The Erase timeout Flag bit (DQ3/DQ11) is reset to ’0’ after a Sector Erase cycle for a period of 100 µs + 20% unless an additional Sector Erase instruction is decoded. After this period, or when the additional Sector Erase instruction is decoded, the Erase timeout flag (DQ3/DQ11) bit is set to 1. 42/129 PSD4235G2 ...
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... PSD4235G2 9 Programming Flash memory Flash memory must be erased prior to being programmed. The MCU may erase Flash memory all at once or by-sector. Although erasing Flash memory occurs on a sector or device basis, programming Flash memory occurs on a word basis. The primary and secondary Flash memories require the MCU to send an instruction to ...
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... READ DQ5 and DQ7 (DQ13 and DQ15) at Valid Even Address DQ7 (DQ15) Yes = Data7 (Data15) No DQ5 No (DQ13 Yes READ DQ7 (DQ15) DQ7 (DQ15) Yes = Data7 (Data15) No Program Program or Erase or Erase Cycle failed Cycle is complete Issue RESET instruction AI04920 Figure 6 PSD4235G2 shows the Data Toggle ...
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... PSD4235G2 since the Toggle Flag bit (DQ6/DQ14) may have changed simultaneously with the Error Flag bit (DQ5/DQ13, see The Error Flag bit (DQ5/DQ13) is set if either an internal timeout occurred while the embedded algorithm attempted to program the MCU attempted to program a ’1’ bit that was not erased (not erased is logic 0) ...
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... Data toggle flowchart 46/129 START READ DQ5 and DQ6 (DQ13 and DQ14) at Valid Even Address DQ6 No (DQ14) = Toggle Yes DQ5 No (DQ13 Yes READ DQ6 (DQ14) DQ6 No (DQ14) = Toggle Yes Program Program or Erase or Erase Cycle failed Cycle is complete Issue RESET instruction AI04921 PSD4235G2 ...
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... PSD4235G2 10 Erasing Flash memory 10.1 Flash Bulk Erase The Flash Bulk Erase instruction uses six WRITE operations followed by a READ operation of the status register, as described in wrong, the Bulk Erase instruction aborts and the device is reset to the Read Memory mode. During a Bulk Erase, the memory status may be checked by reading the Error Flag bit ...
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... If a Suspend Sector Erase instruction was previously executed, the Erase cycle may be resumed with this instruction. The Resume Sector Erase instruction consists of writing 030h to any even address while an appropriate Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3) is high. (See Table 48/129 29.) PSD4235G2 Table 29). This allows reading of ...
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... PSD4235G2 11 Specific features 11.1 Flash Memory Sector Protect Each sector of Primary or Secondary Flash memory can be separately protected against Program and Erase cycles. Sector Protection provides additional data security because it disables all Program or Erase cycles. This mode can be activated (or deactivated) through the JTAG-ISP Port or a device programmer. ...
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... SRAM 12 SRAM The SRAM is enabled when SRAM Select (RS0) from the DPLD is high. SRAM Select (RS0) can contain up to three product terms, allowing flexible memory mapping. SRAM Select (RS0) is configured using PSDsoft Express. 50/129 PSD4235G2 ...
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... PSD4235G2 13 Memory Select signals The Primary Flash Memory Sector Select (FS0-FS7), Secondary Flash Memory Sector Select (CSBOOT0-CSBOOT3) and SRAM Select (RS0) signals are all outputs of the DPLD. They are defined using PSDsoft Express. The following rules apply to the equations for these signals: ● ...
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... Program Select Enable (PSEN, CNTL2) or Read Strobe (RD, CNTL1). For example, to configure the primary Flash memory in Combined space, bits 2 and 4 of the VM register are set to ’1’ (see Figure 52/129 Highest Priority Level 1 SRAM, I/O, or Peripheral I/O Level 2 Secondary Non-Volatile Memory Level 3 Primary Flash Memory Lowest Priority 9). PSD4235G2 AI02867D Figure 8). ...
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... PSD4235G2 13.5 80C51XA memory map example See the Application notes for examples. Figure 8. 8031 memory modules - separate space DPLD RS0 CSBOOT0-3 FS0-FS7 PSEN RD Figure 9. 8031 memory modules - combined space DPLD RD VM REG BIT 3 VM REG BIT 4 PSEN VM REG BIT 1 VM REG BIT 2 ...
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... The Page register can be accessed at address location CSIOP + E0h. Figure 10. Page register 54/129 show the Page register. The eight flip-flops in the register are RESET PGR0 PGR1 PGR2 PGR3 PGR4 PGR5 PGR6 PGR7 PAGE REGISTER PSD4235G2 INTERNAL SELECTS AND LOGIC DPLD AND CPLD PLD AI02871B ...
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... PSD4235G2 15 Memory ID registers The 8-bit Read-only Memory Status registers are included in the CSIOP space. The user can determine the memory configuration of the PSD device by reading the Memory ID0 and Memory ID1 registers. The content of the registers is defined as shown in Table 27. Memory ID registers ...
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... The Turbo bit in PSD The PLDs in the PSD4235G2 can minimize power consumption by switching to standby when inputs remain unchanged for an extended time of about 70 ns. Resetting the Turbo bit to ’0’ (Bit 3 of the PMMR0 register) automatically places the PLDs into standby if no inputs are changing ...
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... PSD4235G2 Table 32. DPLD and CPLD inputs (continued) Input source Page register Macrocell A feedback Macrocell B feedback Flash memory Program Status bit 1. The address inputs are A19-A4 in 80C51XA mode. Input name PGR7-PGR0 MCELLA.FB7-FB0 MCELLB.FB7-FB0 Ready/Busy PLDS Number of signals 57/129 ...
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... PLDS Figure 11. PLD diagram 58/129 PORTS I/O BUS INPUT PLD PSD4235G2 ...
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... PSD4235G2 17 Decode PLD (DPLD) The DPLD, shown in components. The DPLD can be used to generate the following decode signals: ● 8 Sector Select (FS0-FS7) signals for the primary Flash memory (three product terms each) ● 4 Sector Select (CSBOOT0-CSBOOT3) signals for the secondary Flash memory (three product terms each) ● ...
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... Decode PLD (DPLD) Figure 12. DPLD logic array 1. The address inputs are A19-A4 when in 80C51XA mode 2. Additional address lines can be brought ino the PSD via Port 60/129 PSD4235G2 ...
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... PSD4235G2 18 Complex PLD (CPLD) The CPLD can be used to implement system logic functions, such as loadable counters and shift registers, system mailboxes, handshaking protocols, state machines, and random logic. The CPLD can also be used to generate eight External Chip Select (ECS0-ECS7), routed to Port C or Port F. ...
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... MCU ADDRESS / DATA BUS DATA LOAD PT PRESET MCU DATA IN CONTROL MCU LOAD MACROCELL OUT TO MCU D/T Q D/T/JK FF COMB. SELECT /REG SELECT CK CL PSD4235G2 I/O PORTS LATCHED ADDRESS OUT DATA D Q MUX WR CPLD OUTPUT SELECT PDR INPUT D Q DIR WR REG. INPUT MACROCELLS Q ...
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... PSD4235G2 Table 33. Output macrocell Port and Data bit Assignments Output Macrocell Assignment McellA0 McellA1 McellA2 McellA3 McellA4 McellA5 McellA6 McellA7 McellB0 McellB1 McellB2 McellB3 McellB4 McellB5 McellB6 McellB7 18.2 Product Term Allocator The CPLD has a Product Term Allocator. PSDsoft Express, uses the Product Term Allocator to borrow and place product terms from one macrocell to another ...
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... If the output macrocell (OMC) output is declared as an internal node and not as a port pin output in the PSDabel file, then the port pin can be used for other I/O functions. The internal node feedback can be routed as an input to the AND Array. 64/129 Section 20: I/O ports). The flip-flops in each of the 16 output PSD4235G2 ...
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... PSD4235G2 Figure 14. CPLD output macrocell MASK REG. MACROCELL ALLOCATOR POLARITY PT CLK CLKIN FEEDBACK ( .FB ) 18.6 Input macrocells (IMC) The CPLD has 24 input macrocells (IMC), one for each pin on Ports A, B, and C. The architecture of the input macrocells (IMC) is shown in are individually configurable, and can be used as a latch, register pass incoming Port signals prior to driving them onto the PLD input bus ...
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... Slave MCU inputs Read Strobe (RD, CNTL1), Write Strobe (WR/WRL, CNTL0), and Slave_CS. Figure 15. Input macrocell ENABLE ( . FEEDBACK 66/129 INTERNAL DATA BUS INPUT MACROCELL _ RD OUTPUT MACROCELLS A AND MACROCELLS B Q MUX LATCH INPUT MACROCELL PSD4235G2 Figure 17 DIRECTION REGISTER PORT DRIVER PT MUX ALE/AS I/O PIN AI04926 ...
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... PSD4235G2 18.7 External Chip Select The CPLD also provides eight External Chip Select (ECS0-ECS7) outputs that can be used to select external devices. Each External Chip Select (ECS0-ECS7) consists of one product term that can be configured active high or low. The output enable of the pin is controlled by either the output enable product term or the Direction register ...
Page 68
... Complex PLD (CPLD) Figure 17. Handshaking communication using input macrocells 68/129 PSD4235G2 ...
Page 69
... PSD4235G2 19 MCU bus interface The “no-glue logic” MCU Bus Interface block can be directly connected to most popular MCUs and their control signals. Key 16-bit MCUs, with their bus types and control signals, are shown in Table Table 34. MCUs and their control signals ...
Page 70
... Figure 18 shows an example of a system using a MCU with a 16-bit multiplexed bus and a PSD4235G2. The ADIO port on the PSD is connected directly to the MCU address/data bus. Address Strobe (ALE/AS, PD0) latches the address signals internally. Latched addresses can be brought out to Port The PSD drives the ADIO data bus only when one of its internal resources is accessed and Read Strobe (RD, CNTL1) is active ...
Page 71
... Figure 19 shows an example of a system using a MCU with a 16-bit non-multiplexed bus and a PSD4235G2. The address bus is connected to the ADIO Port, and the data bus is connected to Ports F and G. Ports F and G are in tri-state mode when the PSD is not accessed by the MCU. Should the system address bus exceed sixteen bits, Ports may be used for additional address inputs ...
Page 72
... MCU bus interface examples Figure 20 to Figure 25 and some popular MCUs. The PSD4235G2 Control input pins are labeled as to the MCU function for which they are configured. The MCU bus interface is specified using PSDsoft Express. Table 36. 16-bit data bus with WRH and WRL ...
Page 73
... Figure 20, the Intel 80C196 MCU, which has a 16-bit multiplexed address/data bus, is shown connected to a PSD4235G2. The Read Strobe (RD, CNTL1), and Write Strobe (WR/WRL, CNTL0) signals are connected to the CNTL pins. When BHE is not used, the PSD can be configured to receive WRL and Write Enable high-byte (WRH/DBE, PD3) from the MCU ...
Page 74
... RESET 71 PE0 (TMS) 72 PE1 (TCK/ST) 73 PE2 (TDI) 74 PE3 (TDO PE4 (TSTAT/RDY) 76 PE5 (TERR PE6 78 PE7 112 113 114 115 118 119 120 PSD4235G2 D[15:0] A[23:0] VCC_BAR 31 D0 PF0 32 D1 PF1 33 D2 PF2 34 D3 PF3 35 D4 PF4 36 D5 PF5 37 D6 PF6 38 D7 ...
Page 75
... The Philips 80C51XA MCU has a 16-bit multiplexed bus with burst cycles. Address bits (A3- A1) are not multiplexed, while (A19-A4) are multiplexed with data bits (D15-D0). The PSD4235G2 supports the 80C51XA burst mode. The WRH signal is connected to PD3, and WHL is connected to CNTL0. The RD and PSEN signals are connected to the CNTL1 and CNTL2 pins ...
Page 76
... PO14/TIOCA2 105 PO15/TIOCB2/TCL 95 AN0 96 AN1 97 AN2 98 AN3 99 AN4 100 AN5 101 AN6/DA0 102 AN7/DA1 92 ADTRG 116 PG0/CAS/OE 117 PG1/CS3 118 PG2/CS2 119 PG3/CS1 120 PG4/CS0 PSD4235G2 D[15:0] A[23:0] VCC_BAR PSD ADIO0 PF0 ADIO1 PF1 ADIO2 PF2 ADIO3 PF3 ADIO4 PF4 10 36 ...
Page 77
... PSD4235G2 19.9 MMC2001 The Motorola MCORE MMC2001 MCU has a MOD input pin that selects interal or external boot ROM. The PSD can be configured as the external flash boot ROM or as extension to the internal ROM. The MMC2001 has a 16-bit external data bus and 20 address lines with external chip select signals ...
Page 78
... P2.4/CC4IO 52 P2.5/CC5IO 53 P2.6/CC6IO 54 P2.7/CC7IO 57 P2.8/CC8IO/EX0IN 58 P2.9/CC9IO/EX1IN 59 P2.10/CC10IO/EX2IN 60 P2.11/CC11IO/EX3IN 61 P2.12/CC12IO/EX4IN 62 P2.13/CC13IO/EX5IN 63 P2.14/CC14IO/EX6IN 64 P2.15/CC15IO/EX7IN 140 RSTIN 141 RSTOUT 142 NMI PSD4235G2 A[19:16] AD[15:0] VCC_BAR PSD 3 31 ADIO0 PF0 4 32 ADIO1 PF1 5 33 ADIO2 PF2 6 34 ADIO3 PF3 7 35 ADIO4 PF4 10 36 ADIO5 PF5 ...
Page 79
... PSD4235G2 Figure 25. Interfacing the PSD with a C167CR Vcc 144136129109 VccVccVccVccVccVccVccVccVccVcc 138 XTAL1 C167CR 137 XTAL2 65 P3.0/T0IN 66 P3.1/T6OUT 67 P3.2/CAPIN 68 P3.3/T3OUT 69 P3.4/T3UED 70 P3.5/T4IN 73 P3.6/T3IN 74 P3.7/T2IN 75 P3.8/MRST 76 P3.9/MTSR 77 P3.10/TXD0 78 P3.11/RXD0 79 P3.12 80 P3.13/SCLK 81 P3.15/CLKOUT 27 P5.0/AN0 28 P5.1/AN1 29 P5.2/AN2 30 P5.3/AN3 31 P312/BHE/WRH P5.4/AN4 32 P5.5/AN5 33 P5.6/AN6 34 P5.7/AN7 35 P5.8/AN8 36 P5.9/AN9 39 P5 ...
Page 80
... The outputs from the input macrocells (IMC) drive the PLD input bus and can be read by the MCU (see Figure 15: Input 80/129 Figure 28 to Figure 30. In general, once the purpose for a port 26, the ports contain an output multiplexer whose select signals are macrocell). PSD4235G2 Figure 26. Individual Port ...
Page 81
... PSD4235G2 20.2 Port operating modes The I/O Ports have several modes of operation. Some modes can be defined using PSDsoft Express, some by the MCU writing to the registers in CSIOP space, and some by both. The modes that can only be defined using PSDsoft Express must be programmed into the device and cannot be changed unless the device is reprogrammed ...
Page 82
... When the pin is configured as an output, the content of Figure 26). Table 41 for the address output pin assignments on Ports E, F and G Port B Port C Port D Yes Yes Yes Yes No No Yes Yes No Yes Yes Yes PSD4235G2 Port E Port F Port G Yes Yes Yes Yes No No Yes No Yes ( Yes ( Yes ( (A15 - 8) ...
Page 83
... PSD4235G2 Table 39. Port operating modes (continued) Port Mode Port A Address In Yes Data Port No Peripheral I/O Yes JTAG ISP No (2) MCU Reset mode No 1. Can be multiplexed with other I/O functions. 2. Available to Motorola 16-bit 683xx and HC16 families of MCUs. Table 40. Port operating mode settings ...
Page 84
... PSEL0 or PSEL1 is not active. 84/129 Port E Port F (PE7-PE4) (PF3-PF0) Address N/A N/A a7-a4 Address Address a7-a4 a3-a0 (1) Port F Port G (PF7-PF4) (PG3-PG0) Address Address a7-a4 a11-a8 Address Address a7-a4 a11-a8 Figure 27 shows how Port A acts as a bi- PSD4235G2 Port G (PG7-PG4) Address a15-a12 Address a15-a12 ...
Page 85
... PSD4235G2 Figure 27. Peripheral I/O mode RD PSEL0 PSEL1 VM REGISTER BIT 7 WR 20.9 JTAG in-system programming (ISP) Port E is JTAG compliant, and can be used for In-System Programming (ISP). You can multiplex JTAG operations with other functions on Port E because In-System Programming (ISP) is not performed during normal system operation. For more information on the JTAG ...
Page 86
... The addresses in Table 42, are used for setting the Port Port show the Port Architecture diagrams for Ports A/B/C and E/F/G, Table 45. Since Port D only contains four pins, the PSD4235G2 Table 6 are the offsets in Table 42 is 00h. MCU access WRITE/READ WRITE/READ WRITE/READ ...
Page 87
... PSD4235G2 (The slew rate is a measurement of the rise and fall times of an output. A higher slew rate means a faster output response and may create more electrical noise. A pin operates in a high slew rate when the corresponding bit in the Drive register is set to '1.' The default rate is slow slew ...
Page 88
... Output macrocell 88/129 Table 47, are used by the MCU to write data to or read Table 47 shows the register name, the ports having each register type, port). (IMC)). Port READ - input on pin WRITE/READ G READ - outputs of macrocells A, B WRITE - loading macrocells Flip-flop PSD4235G2 Figure 13: MCU Access ...
Page 89
... PSD4235G2 Table 47. Port Data registers Register Name Mask macrocell Input macrocell Enable Out 20.20 Enable Out The Enable Out register can be read by the MCU. It contains the output enable values for a given port. A '1' indicates the driver is in output mode. A '0' indicates the driver is in tri-state and the pin is in input mode ...
Page 90
... PSD Chip Select input (CSI, PD2). Driving this signal high disables the Flash memory, SRAM and CSIOP. ● Write Enable high-byte (WRH, PD3) input DBE input from a MC68HC912. 90/129 DATA OUT OUTPUT MUX DATA IN ENABLE OUT Figure 29. Port D can be configured to perform one or more of PSD4235G2 PORT Pin INPUT MACROCELL AI04936B ...
Page 91
... PSD4235G2 Figure 29. Port D structure DATA OUT Register D WR READ MUX DIR Register D WR 20.23 Port E - functionality and structure Port E can be configured to perform one or more of the following functions (see ● MCU I/O Mode ● In-System Programming (ISP) - JTAG port can be enabled for programming/erase of the PSD device ...
Page 92
... Latched Address output - Provide latched address output as per ● Open Drain - pins can be configured in Open Drain Mode ● Data Port - connected to D15-D8 when Port G is configured as Data Port for a non- multiplexed bus ● MCU Reset Mode - for 16-bit Motorola 683xx and hc16 mcus 92/129 PSD4235G2 Table 41. Table 41. ...
Page 93
... PSD4235G2 Figure 30. Port E, F and G structure DATA OUT Register ADDRESS D Q ALE G Ext. CS (Port F) READ MUX CONTROL Register DIR Register ENABLE PRODUCT TERM ( .OE ) DATA OUT ADDRESS 15:8 ] OUTPUT MUX OUTPUT SELECT DATA IN CPLD-INPUT (Port F) ISP (Port E) I/O ports PORT Pin ...
Page 94
... PLD inputs are changing (zero DC current). Even when inputs do change, significant power can be saved at lower frequencies (AC current), compared to when Turbo mode is on. When the Turbo mode is on, there is a significant DC current component, and the AC component is higher. 94/129 Figure 31: APD 34). unit. PSD4235G2 ...
Page 95
... PSD4235G2 21.1 Automatic Power-down (APD) Unit and Power-down mode The APD Unit, shown in activity of Address Strobe (ALE/AS, PD0). If the APD Unit is enabled, as soon as activity on Address Strobe (ALE/AS, PD0) stops, a four-bit counter starts counting. If Address Strobe (ALE/AS, PD0) remains inactive for fifteen clock periods of CLKIN (PD1), Power-down (PDN) goes high, and the PSD enters Power-down mode, as discussed next ...
Page 96
... APD COUNTER EDGE PD DETECT Memory delay access time No Access PD Table 61, assuming no PLD inputs are changing state and the PLD PSD4235G2 DISABLE BUS INTERFACE Secondary Flash Memory Select Primary Flash Memory Select PLD SRAM Select POWER DOWN (PDN) Select (1) Access recovery time to ...
Page 97
... PSD4235G2 21.5 PSD Chip Select input (CSI, PD2) PD2 of Port D can be configured in PSDsoft Express as PSD Chip Select input (CSI). When low, the signal selects and enables the internal primary Flash memory, secondary Flash memory, SRAM, and I/O blocks for READ or WRITE operations involving the PSD. A high on PSD Chip Select input (CSI, PD2) disables the primary Flash memory, secondary Flash memory, and SRAM, and reduces the PSD power consumption ...
Page 98
... PLD AND Array by setting bits and ’1’ in PMMR2. Table 50. APD counter operation APD Enable bit 98/129 ALE PD ALE level polarity Pulsing PSD4235G2 APD counter Not counting Not counting Counting (Generates PDN after 15 clocks) Counting (Generates PDN after 15 clocks) ...
Page 99
... PSD4235G2 22 Power-on Reset, Warm Reset and Power-down 22.1 Power-on Reset Upon Power-up, the PSD requires a Reset (RESET) pulse of duration t 1 ms) after V is steady. During this period, the device loads internal configurations, clears CC some of the registers and sets the Flash memory into Operating mode. After the rising edge of Reset (RESET), the PSD remains in the Reset mode for an additional period, t (maximum 120 ns), before the first memory access is allowed ...
Page 100
... CC t NLNH-PO Power-On Reset RESET 100/129 Power-On Reset Warm Reset Depends on .re and .pr equations Initialized, based on the selection in PSDsoft Express Configuration menu Cleared to ’0’ t OPR PSD4235G2 Power-down mode Depends on .re and .pr equations Unchanged Unchanged t NLNH t NLNH-A t OPR Warm Reset AI02866b ...
Page 101
... PSD4235G2 23 Programming in-circuit using the JTAG serial interface The JTAG Serial Interface on the PSD can be enabled on Port E (see blocks (primary Flash memory and secondary Flash memory), PLD logic, and PSD Configuration bits may be programmed through the JTAG-ISC Serial Interface. A blank device can be mounted on a printed circuit board and programmed using JTAG In-System Programming (ISP) ...
Page 102
... TSTAT behaves the same as Ready/Busy (PE4) described in (PE4). TSTAT is high when the PSD4235G2 device is in READ mode (primary Flash memory and secondary Flash memory contents can be read). TSTAT is low when Flash memory Program or Erase cycles are in progress, and also when data is being written to the secondary Flash memory ...
Page 103
... PSD4235G2 Table 52. JTAG port signals (continued) Port E pin PE4 PE5 Programming in-circuit using the JTAG serial interface JTAG signals TSTAT Status TERR Error Flag Description 103/129 ...
Page 104
... When delivered from ST, the PSD device has all bits in the memory and PLDs set to '1.' The PSD Configuration register bits are set to '0.' The code, configuration, and PLD logic are loaded using the programming procedure. Information for programming the device is available directly from ST. Please contact your local sales representative. 104/129 PSD4235G2 ...
Page 105
... PSD4235G2 25 Maximum rating Stressing the device above the rating listed in the Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability ...
Page 106
... DC and AC parameters 26 DC and AC parameters These tables describe the AD and DC parameters of the PSD4235G2: ● DC Electrical Specification ● AC timing Specification – PLD timing Combinatorial timing Synchronous clock mode Asynchronous clock mode Input macrocell timing – MCU timing READ timing WRITE timing Peripheral mode timing ...
Page 107
... PSD4235G2 Table 54. Example of PSD typical power calculation at V (Freq PLD) MCU ALE frequency (Freq ALE) % Flash memory Access % SRAM access % I/O access % Normal % Power-down mode (from fitter report total product terms Turbo Mode I total CC 1. This is the operating power with no Flash memory Program or Erase cycles in progress. Calculation is based ...
Page 108
... Freq ALE + % PLD x (from graph using Freq PLD)) = 50µA x 0.90 + 0.1 x (0.8 x 2.5 mA/MHz x 4 MHz + 0.15 x 1.5 mA/MHz x 4 MHz + 24 mA) = 45µ 0.9 + 24) = 45µA + 0.1 x 32.9 = 45µ 3.34 mA PSD4235G2 = 5.0V (with Turbo mode off) CC (ac (dc ( OUT ...
Page 109
... PSD4235G2 Table 56. Operating conditions Symbol V Supply voltage CC Ambient operating temperature (industrial Ambient operating temperature (commercial) Table 57. AC signal letters for PLD timings Letter A Address input C CEout output D Input data E E input G Internal WDOG_ON signal I Interrupt input L ALE input N Reset input or output ...
Page 110
... A Figure 35. AC measurement I/O waveform Figure 36. AC measurement load circuit 110/129 (1) Parameter Test condition OUT ) 3.0V Test Point 0V 2.01 V 195 Ω Device Under Test (Including Scope and Jig Capacitance) PSD4235G2 Min. Max. 30 (2) Typ Max 1.5V AI03103b AI03104b Unit pF Unit ...
Page 111
... PSD4235G2 Figure 37. Switching waveforms - key WAVEFORMS Table 61. DC characteristics Symbol Parameter V input high voltage voltage IH V input low voltage IL RESET high level input V IH1 voltage V RESET low level input voltage IL1 V RESET pin hysteresis HYS V (min) for Flash Erase and CC V LKO ...
Page 112
... V IL1 CC tER -70 Conditions Min Max Min. Typ. Max. 0 400 700 (4) 2.5 3.5 1.5 3.0 is valid at or above 0.8V . IH1 CC tEA AI02863 -90 Fast Turbo PT Off Min Max Aloc PSD4235G2 Unit µA/PT µA/ mA/ MHz mA/ MHz Slew Unit rate (1) – – – – ...
Page 113
... PSD4235G2 Table 62. CPLD Combinatorial timing (continued) Symbol Parameter CPLD register Clear or t ARPW Preset Pulse Width t CPLD Array Delay ARD 1. Fast Slew Rate output available on Port C and Port F. Table 63. CPLD macrocell Synchronous clock mode timing Symbol Parameter Maximum frequency External Feedback ...
Page 114
... MINA Period Figure 39. Synchronous clock mode timing - PLD CLKIN INPUT REGISTERED OUTPUT 114/129 -70 Min Max +t ) 38.4 SA COA +t –10) 62.5 COA +t ) 47.6 CHA CLA 1/f 16 CNTA PSD4235G2 -90 Turbo PT Aloc Off Min Max 26.32 35.71 37. AI02860 Slew Unit rate MHz MHz MHz – 2 ...
Page 115
... PSD4235G2 Figure 40. Asynchronous RESET / Preset RESET/PRESET INPUT REGISTER OUTPUT Figure 41. Asynchronous clock mode timing (product term clock) CLOCK INPUT REGISTERED OUTPUT Figure 42. Input macrocell timing (product term clock) PT CLOCK INPUT OUTPUT AI03101 Table 65. Input macrocell timing Symbol Parameter t Input setup time ...
Page 116
... The polling status, DQ7, is valid tQ7VQV time units before the data byte, DQ0-DQ7, is valid for reading. 3. DQ7 is DQ15 for Motorola MCU with 16-bit data bus. Figure 43. Peripheral I/O write timing ALE/ BUS WR 116/129 Parameter (pre-programmed) ADDRESS tWLQV (PF) PSD4235G2 Min. Typ. Max. 8 2.2 14 ...
Page 117
... PSD4235G2 Figure 44. READ timing ALE / MULTIPLEXED BUS ADDRESS NON-MULTIPLEXED BUS DATA NON-MULTIPLEXED BUS CSI RD (PSEN, DS AVPV 1. t and t are not required for 80C251 in Page Mode or 80C51XA in Burst Mode. AVLX LXAX Table 67. READ timing Symbol Parameter t ALE or AS Pulse Width LVLX t Address setup time ...
Page 118
... RD and PSEN have the same timing timing has the same timing as DS, LDS, UDS, and PSEN signals multiplexed mode, latched addresses generated from ADIO delay to address output on any Port. 118/129 -70 Conditions Min Max 0 (5) 20 PSD4235G2 -90 Turbo Unit Off Min Max ...
Page 119
... PSD4235G2 Figure 45. WRITE timing ALE MULTIPLEXED BUS ADDRESS NON-MULTIPLEXED BUS DATA NON-MULTIPLEXED BUS CSI WR (DS Table 68. WRITE timing Symbol Parameter t ALE or AS Pulse Width LVLX t Address setup time AVLX t Address Hold time LXAX Address Valid to Leading t AVWL Edge Valid to Leading edge of WR ...
Page 120
... Assuming data is stable before active WRITE signal. Figure 46. Peripheral I/O read timing ALE / BUS CSI RD 120/129 Conditions (2) (2)(5) (6) (2)(7) ADDRESS t AVQV ( PF) t SLQV (PF) t RLQV (PF) t RLRH (PF) DATA ON PORT F PSD4235G2 -70 -90 Min Max Min Max DATA VALID t QXRH ( PF) t RHQZ ( PF) ...
Page 121
... PSD4235G2 Table 69. Port F Peripheral Data Mode Read timing Symbol Parameter t Address Valid to Data Valid AVQV–PF t CSI Valid to Data Valid SLQV– Data Valid t RLQV– Data Valid 8031 Mode t Data In to Data Out Valid DVQV– Data Hold time QXRH–PF ...
Page 122
... Signal the period of CLKIN (PD1). CLCL Figure 48. ISC timing t TCK TDI/TMS ISC OUTPUTS/TDO ISC OUTPUTS/TDO 122/129 Conditions Conditions Using CLKIN (PD1) ISCCH t ISCCL t t ISCPSU ISCPH PSD4235G2 Min Max 25 120 -70 -90 Min Max Min Max CLCL t ISCPZV t ISCPCO t ISCPVZ AI02865 Unit μ ...
Page 123
... PSD4235G2 Table 73. ISC timing Symbol Parameter Clock (TCK, PC1) frequency (except for t ISCCF PLD) Clock (TCK, PC1) high time (except for t ISCCH PLD) Clock (TCK, PC1) low time (except for t ISCCL PLD) t Clock (TCK, PC1) frequency (PLD only) ISCCFP t Clock (TCK, PC1) high time (PLD only) ...
Page 124
... PSD4235G2 ccc inches Typ Min – – – 0.0020 0.0550 0.0530 0.0090 0.0070 – 0.0040 0.5510 – ...
Page 125
... PSD4235G2 Table 74. LQFP80 - 80-lead plastic thin, quad, flat package mechanical data Symb ccc 1. Values in inches are converted from mm and rounded to 4 decimal digits. mm Typ Min Max 0.600 0.450 0.750 1.000 – – 0° 7° 0.080 Package mechanical (1) inches Typ Min Max ...
Page 126
... Option T = Tape & Reel Packing 1. The 3.3V±10% devices are not covered by this data sheet, but by the PSD4235G2V data sheet. For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you. ...
Page 127
... PSD4235G2 Appendix A Pin assignments Table 76. PSD4235G2 LQFP80 Pin Pin No. Pin No. Pin assignments Pin No. assignments 1 PD2 21 2 PD3 22 3 AD0 23 4 AD1 24 5 AD2 25 6 AD3 26 7 AD4 27 8 GND AD5 30 11 AD6 31 12 AD7 32 13 AD8 33 14 AD9 34 15 AD10 35 16 ...
Page 128
... Table 75) Document reformatted. SRAM standby mode and backup battery feature removed. All products are delivered in ECOPACK-compliant packages. Changed TQFP80 into LQFP80 and updated 4 mechanical. Small text changes. Regrouped sections AC/DC parameters, and DC and AC parameters. PSD4235G2 Changes Table Section 27: Package 74, ...
Page 129
... PSD4235G2 Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...