IDT7024S55J IDT, Integrated Device Technology Inc, IDT7024S55J Datasheet
IDT7024S55J
Specifications of IDT7024S55J
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IDT7024S55J Summary of contents
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... Features True Dual-Ported memory cells which allow simultaneous reads of the same memory location High-speed access – Military: 20/25/35/55/70ns (max.) – Industrial: 55ns (max.) – Commercial: 15/17/20/25/35/55ns (max.) Low-power operation – IDT7024S Active: 750mW (typ.) Standby: 5mW (typ.) – IDT7024L Active: 750mW (typ.) Standby: 1mW (typ ...
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... This device provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature controlled by chip enable (CE) permits the on-chip circuitry of each Pin Configurations ...
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IDT7024S/L High-Speed Dual-Port Static RAM Pin Configurations (1,2, I/O I I/O I/O 10L I/O 11L I I/O I/O 13L I/O I/O ...
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IDT7024S/L High-Speed Dual-Port Static RAM Truth Table I: Non-Contention Read/Write Control (1) Inputs R ...
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IDT7024S/L High-Speed Dual-Port Static RAM Capacitance (T = +25° 1.0MHz) A Symbol Parameter Conditions C Input Capacitance IN C Output Capacitance V OUT NOTES: 1. This parameter are determined by device characterization, but is not ...
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IDT7024S/L High-Speed Dual-Port Static RAM DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol Parameter Dynamic Operating CC Current Outputs Disabled SEM = V (Both Ports Active ...
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IDT7024S/L High-Speed Dual-Port Static RAM Data Retention Waveform 4. CDR Test Conditions Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load DATA OUT BUSY ...
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IDT7024S/L High-Speed Dual-Port Static RAM AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol Parameter READ CYCLE t Read Cycle Time RC t Address Access Time AA (3) t Chip Enable Access Time ACE ...
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IDT7024S/L High-Speed Dual-Port Static RAM Waveform of Read Cycles ADDR CE OE UB, LB R/W DATA OUT BUSY OUT NOTES: 1. Timing depends on which signal is asserted last, CE, OE, LB, or UB. 2. Timing depends ...
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IDT7024S/L High-Speed Dual-Port Static RAM AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Symbol Parameter WRITE CYCLE t Write Cycle Time WC (3) t Chip Enable to End-of-Write EW t Address Valid to End-of-Write AW ...
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... R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the access Semaphore 6.42 11 (1,5, for memory array writing cycle. IL for ( allow the I/O drivers to turn off and data & and SEM = must 2740 drw 09 (1,5) 2740 drw 10 ...
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IDT7024S/L High-Speed Dual-Port Static RAM Timing Waveform of Semaphore Read after Write Timing, Either Side VALID ADDRESS t AW SEM I R/W OE NOTES ...
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IDT7024S/L High-Speed Dual-Port Static RAM AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol Parameter BUSY TIMING (M BUSY Access Time from Address Match t BAA BUSY Disable Time from ...
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IDT7024S/L High-Speed Dual-Port Static RAM Timing Waveform of Write with Port-to-Port Read and BUSY ADDR "A" R/W "A" DATA IN "A" (1) t APS ADDR "B" BUSY "B" DATA OUT "B" NOTES ensure that the ...
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IDT7024S/L High-Speed Dual-Port Static RAM Waveform of BUSY Arbitration Controlled by CE Timing ADDR "A" and "B" CE "A" (2) t APS CE "B" BUSY "B" Waveform of BUSY Arbitration Cycle Controlled by Address Match Timing (M/S ...
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IDT7024S/L High-Speed Dual-Port Static RAM Waveform of Interrupt Timing ADDR "A" "A" R/W "A" INT "B" ADDR "B" "B" OE "B" INT "B" NOTES: 1. All timing is the same for ...
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... interrupt flag (INT FFF (HEX) and to clear the interrupt flag (INT the memory location FFF. The message (16 bits) at FFE or FFF is user- defined, since addressable SRAM location. If the interrupt function 6.42 17 outputs on the IDT7024 are X and BUSY outputs cannot be LOW simultaneously. ...
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... IDT7024S/L High-Speed Dual-Port Static RAM is not used, address locations FFE and FFF are not used as mail boxes, but as part of the random access memory. Refer to Truth Table III for the interrupt operation. Busy Logic Busy Logic provides a hardware indication that both ports of the RAM have accessed the same location at the same time. It also allows one of the two accesses to proceed and signals the other side that the RAM is “ ...
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... Semaphore 0 could be used to indicate the side which would control the lower section of memory, and Semaphore 1 could be defined as the indicator for the upper section of memory. To take a resource, in this example the lower 2K of Dual-Port RAM, the processor on the left port could write and then read a zero in to Semaphore 0 ...
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... Semaphores are a useful form of arbitration in systems like disk interfaces where the CPU must be locked out of a section of memory during a transfer and the I/O device cannot tolerate any wait states. With the use of semaphores, once the two devices has determined which memory area was “ ...
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IDT7024S/L High-Speed Dual-Port Static RAM Ordering Information XXXXX A 999 Device Power Speed Package Type NOTE: 1. Industrial temperature range is available on selected PLCC packages in standard power. For other speeds, packages and powers contact your ...
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IDT7024S/L High-Speed Dual-Port Static RAM Datasheet Document History (continued) 9/12/01: Page 2 & 3 Added date revision for pin configurations Page 5 Added Industrial temp to the column heading for 20ns to DC Electrical Characteristics Pages 8,10,13&15 ...