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IDT71T75702S85PFI8
IDT71T75702S85PFI8 | |
|---|---|
| Manufacturer Part Number | IDT71T75702S85PFI8 |
| Description | IC SRAM 18MBIT 85NS 100TQFP |
| Manufacturer | IDT, Integrated Device Technology Inc |
| IDT71T75702S85PFI8 datasheets |
|
Availability: By request
International delivery:
Warranty: 60 days
×
- We provide standard 60-days warranty for all parts. If warranty differs we always mention it beforehand. In case of return we cover shipping costs.
- If you still have any questions - please contact us
×
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Specifications of IDT71T75702S85PFI8 | |||
|---|---|---|---|
| Format - Memory | RAM | Memory Type | SRAM - Synchronous ZBT |
| Memory Size | 18M (512K x 36) | Speed | 85ns |
| Interface | Parallel | Voltage - Supply | 2.375 V ~ 2.625 V |
| Operating Temperature | -40°C ~ 85°C | Package / Case | 100-TQFP, 100-VQFP |
| Lead Free Status / RoHS Status | Contains lead / RoHS non-compliant | Other names | 71T75702S85PFI8 |
PrevNext
512K x 36, 1M x 18 memory configurations
Supports high performance system speed - 100 MHz
(7.5 ns Clock-to-Data Access)
TM
ZBT
Feature - No dead cycles between write and read cycles
Internally synchronized output buffer enable eliminates the
need to control OE
OE
OE
OE
OE
Single R/W W W W W (READ/WRITE) control pin
4-word burst capability (Interleaved or linear)
BW
BW
BW
BW
BW
BW
BW
- BW
BW
Individual byte write (BW
) control (May tie active)
1
4
Three chip enables for simple depth expansion
2.5V power supply (±5%)
2.5V (±5%) I/O Supply (V
)
DDQ
Power down controlled by ZZ input
Boundary Scan JTAG Interface (IEEE 1149.1 Compliant)
Packaged in a JEDEC standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA)
The IDT71T75702/902 are 2.5V high-speed 18,874,368-bit
(18 Megabit) synchronous SRAMs organized as 512K x 36 /1M x 18.
They are designed to eliminate dead bus cycles when turning the bus
around between reads and writes, or writes and reads. Thus they have
TM
been given the name ZBT
, or Zero Bus Turnaround.
Address and control signals are applied to the SRAM during one clock
cycle, and on the next clock cycle the associated data cycle occurs, be
it read or write.
A
-A
Address Inputs
0
19
Chip Enables
, CE
,
1
2
2
Output Enable
R/
Read/Write Signal
Clock Enable
Individual Byte Write Selects
,
,
,
1
2
3
4
CLK
Clock
ADV/
Advance Burst Address/Load New Address
Linear/Interleaved Burst Order
TMS
Test Mode Select
TDI
Test Data Input
TCK
Test Clock
TDO
Test Data Output
JTAG Reset (Optional)
ZZ
Sleep Mode
I/O
-I/O
, I/O
-I/O
Data Input/Output
0
31
P1
P4
V
, V
Core Power, I/O Power
DD
DDQ
V
Ground
SS
©2004 Integrated Device Technology, Inc.
512K x 36, 1M x 18
2.5V Synchronous ZBT™ SRAMs
2.5V I/O, Burst Counter
Flow-Through Outputs
The IDT71T75702/902 contain address, data-in and control signal
registers. The outputs are flow-through (no output data register). Output
enable is the only asynchronous signal and can be used to disable the
outputs at any given time.
A Clock Enable (CEN) pin allows operation of the IDT71T75702/902
to be suspended as long as necessary. All synchronous inputs are
ignored when CEN is high and the internal device registers will hold their
previous values.
There are three chip enable pins (CE
user to deselect the device when desired. If any one of these three is not
asserted when ADV/LD is low, no new memory operation can be initiated.
However, any pending data transfers (reads or writes) will be completed.
The data bus will tri-state one cycle after the chip is deselected or a write
is initiated.
The IDT71T75702/902 have an on-chip burst counter. In the burst
mode, the IDT71T75702/902 can provide four cycles of data for a single
address presented to the SRAM. The order of the burst sequence is
defined by the LBO input pin. The LBO pin selects between linear and
interleaved burst sequence. The ADV/LD signal is used to load a new
external address (ADV/LD = LOW) or increment the internal burst counter
(ADV/LD = HIGH).
The IDT71T75702/902 SRAMs utilize IDT’s high-performance
CMOS process, and are packaged in a JEDEC Standard 14mm x 20mm
100-pin plastic thin quad flatpack (TQFP) as well as a 119 ball grid array
(BGA).
1
IDT71T75702
IDT71T75902
, CE
, CE
) that allow the
1
2
2
Input
Synchronous
Input
Synchronous
Input
Asynchronous
Input
Synchronous
Input
Synchronous
Input
Synchronous
Input
N/A
Input
Synchronous
Input
Static
Input
N/A
Input
N/A
Input
N/A
Output
N/A
Input
Asynchronous
Input
Synchronous
I/O
Synchronous
Supply
Static
Supply
Static
5319 tbl 01
FEBRUARY 2009
DSC-5319/08
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IDT71T75702S85BGI8 |
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IDT71T75702S75PF |
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|
IDT71T75702S85PFI8 Summary of contents |
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