27C512AT-15/SO Microchip Technology, 27C512AT-15/SO Datasheet - Page 5

IC OTP 512KBIT 150NS 28SOIC

27C512AT-15/SO

Manufacturer Part Number
27C512AT-15/SO
Description
IC OTP 512KBIT 150NS 28SOIC
Manufacturer
Microchip Technology
Datasheet

Specifications of 27C512AT-15/SO

Format - Memory
EPROMs
Memory Type
OTP EPROM
Memory Size
512K (64K x 8)
Speed
150ns
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Package / Case
28-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
1.2
(See Timing Diagrams and AC Characteristics)
Read Mode is accessed when
a)
b)
FIGURE 1-2:
TABLE 1-6:
Read
Program
Program Verify
Program Inhibit
Standby
Output Disable
Identity
X = Don’t Care
2004 Microchip Technology Inc.
the CE pin is low to power up (enable) the chip
the OE/V
output pins
Operation Mode
Read Mode
Address
OE/V
Notes:
Data
V
PP
CE
CC
PP
pin is low to gate the data to the
PROGRAMMING WAVEFORMS (1)
MODES
13.0 V (3)
V
(1)
(2)
(3)
V
V
V
V
6.5 V (3)
5.0V
V
V
IL
IH
IL
IH
IL
IH
IL
The input timing reference level is 0.8V for V
t
V
DF
CC
and t
t
= 6.5V ±0.25V, V
PRT
OE
t
CES
are characteristics of the device but must be accommodated by the programmer.
CE
V
V
V
V
V
V
V
t
t
t
t
VCS
OES
AS
IH
IH
DS
IL
IL
IL
IL
IL
PP
= V
Address Stable
Data In Stable
H
= 13.0V ±0.5V for express programming algorithm.
t
t
OPW
PW
Program
OE/V
V
V
V
V
V
V
X
IH
IL
IL
IL
H
H
PP
t
OEH
t
For Read operations, if the addresses are stable, the
address access time (t
CE to output (t
after a delay (t
DH
IL
and 2.0V for V
t
OR
A9
V
X
X
X
X
X
X
H
OE
CE
IH
) from the falling edge of OE/V
.
). Data is transferred to the output
t
(2)
CE
ACC
) is equal to the delay from
Verify
Data Out Valid
Identity Code
27C512A
O0 - O7
High Z
High Z
High Z
D
D
D
OUT
OUT
IN
DS11173G-page 5
t
t
(2)
DF
AH
PP
.

Related parts for 27C512AT-15/SO