27C512AT-20/L Microchip Technology, 27C512AT-20/L Datasheet - Page 6

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27C512AT-20/L

Manufacturer Part Number
27C512AT-20/L
Description
IC OTP 512KBIT 200NS 32PLCC
Manufacturer
Microchip Technology
Datasheet

Specifications of 27C512AT-20/L

Format - Memory
EPROMs
Memory Type
OTP EPROM
Memory Size
512K (64K x 8)
Speed
200ns
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Package / Case
32-PLCC
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
27C512A
1.3
The standby mode is entered when the CE pin is high,
and the program mode is not identified.
When this conditions are met, the supply current will
drop from 25 mA to 30 A.
1.4
This multifunction pin eliminates bus connection in mul-
tiple bus microprocessor systems and the outputs go to
high impedance when:
• the OE/V
When a V
programming voltage (V
1.5
Windowed products offer the ability to erase the mem-
ory array. The memory matrix is erased to the all “1's”
state as a result of being exposed to ultraviolet light. To
ensure complete erasure, a dose of 15 watt-second/
cm
must be placed within one inch and directly underneath
an ultraviolet lamp with a wavelength of 2537 Ang-
stroms, intensity of 12,000 mW/cm
40 minutes.
1.6
The Express algorithm must be used for best results. It
has been developed to improve programming yields
and throughput times in a production environment. Up
to 10 100-microsecond pulses are applied until the byte
is verified. A flowchart of the Express algorithm is
shown in Figure 1-3.
Programming takes place when:
a)
b)
c)
DS11173G-page 6
2
V
OE/V
CE line is low.
is required. This means that the device window
CC
Standby Mode
Output Enable OE/V
Erase Mode (UV Windowed Versions)
Programming Mode
is brought to the proper voltage,
PP
H
PP
input is applied to this pin, it supplies the
is brought to the proper V
pin is high (V
PP
) to the device.
IH
).
PP
2
for approximately
H
level, and
Since the erased state is “1” in the array, programming
of “0” is required. The address to be programmed is set
via pins A0 - A15 and the data to be programmed is
presented to pins O0 - O7. When data and address are
stable, a low going pulse on the CE line programs that
location.
1.7
After the array has been programmed it must be veri-
fied to ensure all the bits have been correctly pro-
grammed. This mode is entered when all the following
conditions are met:
a)
b)
c)
1.8
When programming multiple devices in parallel with dif-
ferent data, only CE needs to be under separate control
to each device. By pulsing the CE line low on a partic-
ular device, that device will be programmed; all other
devices with CE held high will not be programmed with
the data (although address and data will be available
on their input pins).
1.9
In this mode specific data is output which identifies the
manufacturer as Microchip Technology Inc. and the
device type. This mode is entered when Pin A9 is
taken to V
must be at V
non-erasable bytes whose data appears on O0 through
O7.
Pin
Manufacturer
Device Type*
* Code subject to change
Identity
V
the OE/V
the CE line is low.
CC
Verify
Inhibit
Identity Mode
is at the proper level,
H
(11.5V to 12.5V). The CE and OE/V
IL
PP
. A0 is used to access any of the two
Input
pin is low, and
V
A0
V
IH
IL
0
1
0
7
2004 Microchip Technology Inc.
O
0
0
6
O
1
0
5
O
0
0
4
Output
O
1
1
3
O
0
1
2
O
0
0
1
PP
1
0
O
0
lines
29
0D
H
e
x

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