AT28BV64B-20SC Atmel, AT28BV64B-20SC Datasheet - Page 4
Manufacturer Part Number
IC EEPROM 64KBIT 200NS 28SOIC
Specifications of AT28BV64B-20SC
Format - Memory
EEPROMs - Parallel
64K (8K x 8)
Voltage - Supply
2.7 V ~ 3.6 V
0°C ~ 70°C
Package / Case
28-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Software Data Protection
The AT28BV64B features DATA Polling to indicate the end of a write cycle. During a byte or
page write cycle an attempted read of the last byte written will result in the complement of the
written data to be presented on I/O7. Once the write cycle has been completed, true data is valid
on all outputs, and the next write cycle may begin. DATA Polling may begin at anytime during the
In addition to DATA Polling, the AT28BV64B provides another method for determining the end of
a write cycle. During the write operation, successive attempts to read data from the device will
result in I/O6 toggling between one and zero. Once the write has completed, I/O6 will stop tog-
gling and valid data will be read. Reading the toggle bit may begin at any time during the write
If precautions are not taken, inadvertent writes may occur during transitions of the host system
power supply. Atmel
memory against inadvertent writes.
Hardware features protect against inadvertent writes to the AT28BV64B in the following ways:
out 10 ms (typical) before allowing a write; (b) write inhibit – holding any one of OE low, CE high
or WE high inhibits write cycles; and (c) noise filter – pulses of less than 15 ns (typical) on the
WE or CE inputs will not initiate a write cycle.
A software-controlled data protection feature has been implemented on the AT28BV64B. Soft-
ware data protection (SDP) helps prevent inadvertent writes from corrupting the data in the
device. SDP can prevent inadvertent writes during power-up and power-down as well as any
other potential periods of system instability.
The AT28BV64B can only be written using the software data protection feature. A series of three
write commands to specific addresses with specific data must be presented to the device before
writing in the byte or page mode. The same three write commands must begin each write opera-
tion. All software write commands must obey the page mode write timing specifications. The
data in the 3-byte command sequence is not written to the device; the addresses in the com-
mand sequence can be utilized just like any other location in the device.
Any attempt to write to the device without the 3-byte sequence will start the internal write timers.
No data will be written to the device; however, for the duration of t
tively be polling operations.
An extra 64 bytes of EEPROM memory are available to the user for device identification. By rais-
ing A9 to 12V ± 0.5V and using address locations 7FC0H to 7FFFH, the additional bytes may be
written to or read from in the same manner as the regular memory array.
power-on delay – once V
has incorporated both hardware and software features that will protect the
has reached 1.8V (typical) the device will automatically time
, read operations will effec-