IC EEPROM 64KBIT 200NS 28TSOP

AT28BV64B-20TI

Manufacturer Part NumberAT28BV64B-20TI
DescriptionIC EEPROM 64KBIT 200NS 28TSOP
ManufacturerAtmel
AT28BV64B-20TI datasheet
 


Specifications of AT28BV64B-20TI

Format - MemoryEEPROMs - ParallelMemory TypeEEPROM
Memory Size64K (8K x 8)Speed200ns
InterfaceParallelVoltage - Supply2.7 V ~ 3.6 V
Operating Temperature-40°C ~ 85°CPackage / Case28-TSOP
Lead Free Status / RoHS StatusContains lead / RoHS non-compliant  
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3. Block Diagram
4. Device Operation
4.1
Read
The AT28BV64B is accessed like a static RAM. When CE and OE are low and WE is high, the
data stored at the memory location determined by the address pins is asserted on the outputs.
The outputs are put in the high impedance state when either CE or OE is high. This dual-line
control gives designers flexibility in preventing bus contention in their systems.
4.2
Byte Write
A low pulse on the WE or CE input with CE or WE low (respectively) and OE high initiates a write
cycle. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is
latched by the first rising edge of CE or WE. Once a byte write has been started, it will automati-
cally time itself to completion. Once a programming operation has been initiated and for the
duration of t
4.3
Page Write
The page write operation of the AT28BV64B allows 1 to 64 bytes of data to be written into the
device during a single internal programming period. A page write operation is initiated in the
same manner as a byte write; the first byte written can then be followed by 1 to 63 additional
bytes. Each successive byte must be written within 100 µs (t
limit is exceeded, the AT28BV64B will cease accepting data and commence the internal pro-
gramming operation. All bytes during a page write operation must reside on the same page as
defined by the state of the A6 to A12 inputs. For each WE high to low transition during the page
write operation, A6 to A12 must be the same.
The A0 to A5 inputs specify which bytes within the page are to be written. The bytes may be
loaded in any order and may be altered within the same load period. Only bytes which are spec-
ified for writing will be written; unnecessary cycling of other bytes within the page does not occur.
0299I–PEEPR–4/09
, a read operation will effectively be a polling operation.
WC
) of the previous byte. If the t
BLC
BLC
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