AT28C256E-15PC Atmel, AT28C256E-15PC Datasheet - Page 4

IC EEPROM 256KBIT 150NS 28DIP

AT28C256E-15PC

Manufacturer Part Number
AT28C256E-15PC
Description
IC EEPROM 256KBIT 150NS 28DIP
Manufacturer
Atmel
Datasheets

Specifications of AT28C256E-15PC

Format - Memory
EEPROMs - Parallel
Memory Type
EEPROM
Memory Size
256K (32K x 8)
Speed
150ns
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Package / Case
28-DIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
AT28C256E15PC

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT28C256E-15PC
Manufacturer:
ATMEL
Quantity:
200
4.5
4.6
4.6.1
4.6.2
4.7
4.8
4
Toggle Bit
Data Protection
Device Identification
Optional Chip Erase Mode
AT28C256
Hardware Protection
Software Data Protection
In addition to DATA Polling the AT28C256 provides another method for determining the end of a
write cycle. During the write operation, successive attempts to read data from the device will
result in I/O6 toggling between one and zero. Once the write has completed, I/O6 will stop tog-
gling and valid data will be read. Reading the toggle bit may begin at any time during the write
cycle.
If precautions are not taken, inadvertent writes may occur during transitions of the host system
power supply. Atmel has incorporated both hardware and software features that will protect the
memory against inadvertent writes.
Hardware features protect against inadvertent writes to the AT28C256 in the following ways: (a)
V
once V
a write; (c) write inhibit – holding any one of OE low, CE high or WE high inhibits write cycles;
and (d) noise filter – pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a
write cycle.
A software controlled data protection feature has been implemented on the AT28C256. When
enabled, the software data protection (SDP), will prevent inadvertent writes. The SDP feature
may be enabled or disabled by the user; the AT28C256 is shipped from Atmel with SDP
disabled.
SDP is enabled by the host system issuing a series of three write commands; three specific
bytes of data are written to three specific addresses (refer to “Software Data Protection” algo-
rithm). After writing the 3-byte command sequence and after t
protected against inadvertent write operations. It should be noted, that once protected the host
may still perform a byte or page write to the AT28C256. This is done by preceding the data to be
written by the same 3-byte command sequence used to enable SDP.
Once set, SDP will remain active unless the disable command sequence is issued. Power transi-
tions do not disable SDP and SDP will protect the AT28C256 during power-up and power-down
conditions. All command sequences must conform to the page write timing specifications. The
data in the enable and disable command sequences is not written to the device and the memory
addresses used in the sequence may be written with data in either a byte or page write
operation.
After setting SDP, any attempt to write to the device without the 3-byte command sequence will
start the internal write timers. No data will be written to the device; however, for the duration of
t
An extra 64 bytes of EEPROM memory are available to the user for device identification. By rais-
ing A9 to 12V ± 0.5V and using address locations 7FC0H to 7FFFH the additional bytes may be
written to or read from in the same manner as the regular memory array.
The entire device can be erased using a 6-byte software code. Please see “Software Chip
Erase” application note for details.
WC
CC
, read operations will effectively be polling operations.
sense – if V
CC
has reached 3.8V the device will automatically time out 5 ms (typical) before allowing
CC
is below 3.8V (typical) the write function is inhibited; (b) V
WC
the entire AT28C256 will be
CC
power-on delay –
0006M–PEEPR–12/09

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