AT25256AW-10SU-2.7 Atmel, AT25256AW-10SU-2.7 Datasheet
AT25256AW-10SU-2.7
Specifications of AT25256AW-10SU-2.7
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AT25256AW-10SU-2.7 Summary of contents
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... Description The AT25128A/256A provides 131,072/262,144 bits of serial electrically-erasable pro- grammable read only memory (EEPROM) organized as 16,384/32,768 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The devices are available in space saving 8-lead PDIP, 8-lead EIAJ SOIC, 8-lead JEDEC SOIC, 8-lead TSSOP, 8-ball dBGA2 and 8-lead SAP packages ...
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Table 0-1. Pin Configurations Pin Name Function CS Chip Select SCK Serial Data Clock SI Serial Data Input SO Serial Data Output GND Ground VCC Power Supply WP Write Protect HOLD Suspends Serial Input NC No Connect Block Write protection ...
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Figure 1-1. Block Diagram (1) Table 1-1. Pin Capacitance Applicable over recommended operating range from T Symbol Test Conditions C Output Capacitance (SO) OUT C Input Capacitance (CS, SCK, SI, WP, HOLD) IN Note: 1. This parameter is characterized and ...
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Table 1-2. DC Characteristics Applicable over recommended operating range from T 40C to +125 +1.8V to +5.5V(unless otherwise noted Symbol Parameter V Supply Voltage CC1 V Supply Voltage CC2 V Supply Voltage CC3 ...
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Table 1-3. AC Characteristics Applicable over recommended operating range from TTL Gate and 30 pF (unless otherwise noted) Symbol Parameter f SCK Clock Frequency SCK t Input Rise Time RI t Input Fall Time FI t ...
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... Hold to Output High Output Disable Time DIS t Write Cycle Time WC (1) Endurance 5.0V, 25C, Page Mode Notes: 1. This parameter is characterized and is not 100% tested. Contact Atmel for further information. AT25128A_256A 6 = 40 85 40C to +125 Voltage Min 4.55.5 2.7 ...
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Serial Interface Description MASTER: The device that generates the serial clock. SLAVE: Because the serial clock pin (SCK) is always an input, the AT25128A/256A always operates as a slave. TRANSMITTER/RECEIVER: The AT25128A/256A has separate pins designated for data transmission ...
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Figure 2-1. SPI Serial Interface AT25128A_256A 8 AT25128A/256A 3368J–SEEPR–06/07 ...
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... Set Write Enable Latch 0000 X100 Reset Write Enable Latch 0000 X101 Read Status Register 0000 X001 Write Status Register 0000 X011 Read Data from Memory Array 0000 X010 Write Data to Memory Array Status Register Format Bit 6 Bit 5 Bit 4 Bit BP1 ...
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... WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select one of four levels of protection. The AT25128A/256A is divided into four array segments. Top quarter (1/4), top half (1/2), or all of the memory segments can be protected. Any of the data within any selected segment will therefore be read only. The block write protection levels and correspond- ...
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... WRITE SEQUENCE (WRITE): In order to program the AT25128A/256A, two separate instruc- tions must be executed. First, the device must be write enabled via the Write Enable (WREN) Instruction ...
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Timing Diagrams (for SPI Mode 0 (0, 0)) Figure 4-1. Synchronous Data Timing CSS V IH SCK HI Figure ...
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Figure 4-3. WRDI Timing Figure 4-4. RDSR Timing CS 0 SCK SI INSTRUCTION HIGH IMPEDANCE SO Figure 4-5. WRSR Timing 3368J–SEEPR–06/ MSB AT25128A_256A ...
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Figure 4-6. READ Timing Figure 4-7. WRITE Timing Figure 4-8. HOLD Timing CS SCK HOLD SO AT25128A_256A 3368J–SEEPR–06/07 ...
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AT25128A Ordering Information Ordering Code (2) AT25128A-10PU-2.7 (2) AT25128A-10PU-1.8 (2) AT25128AN-10SU-2.7 (2) AT25128AN-10SU-1.8 (2) AT25128AW-10SU-2.7 (2) AT25128AW-10SU-1.8 (2) AT25128A-10TU-2.7 (2) AT25128A-10TU-1.8 (2) AT25128AU2-10UU-1.8 (2) AT25128AY7-10YH-1.8 (3) AT25128A-W1.8-11 Notes: 1. For 2.7V devices used in the 4.5V to 5.5V range, ...
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... AT25256A Ordering Information Ordering Code (2) AT25256A-10PU-2.7 (2) AT25256A-10PU-1.8 (2) AT25256AN-10SU-2.7 (2) AT25256AN-10SU-1.8 (2) AT25256AW-10SU-2.7 (2) AT25256AW-10SU-1.8 (2) AT25256A-10TU-2.7 (2) AT25256A-10TU-1.8 (2) AT25256AU2-10UU-1.8 (2) AT25256AY7-10YH-1.8 (3) AT25256A-W1.8-11 Notes: 1. For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC Characteristics tables. 2. “U” designates Green package + RoHS compliant. 3. Available in waffle pack and wafer form; order as SL788 for wafer form. Bumped die available upon request. Please contact Serial Interface Marketing ...
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Packaging Information 8P3 – PDIP Top View PLCS Side View Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA, for additional information. 2. Dimensions A and L are ...
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JEDEC SOIC TOP VIEW TOP VIEW e e SIDE VIEW SIDE VIEW Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. 1150 E. Cheyenne Mtn. Blvd. ...
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EIAJ SOIC 1 N Top View e D Side View Notes: 1. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information. 2. Mismatch of the upper and lower dies and resin burrs ...
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A1 BALL PAD CORNER e (e1) 1. Dimension 'b' is measured at the maximum solder ball diameter. This drawing is for general information only. 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 R AT25128A_256A 20 D ...
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TSSOP Pin 1 indicator this corner N Top View Side View Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances, datums, ...
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UTSAP PIN 1 INDEX AREA D E 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 R AT25128A_256A 22 A PIN COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN A – A1 ...
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Revision History Doc. Rev. 3368J 3368I 3368J–SEEPR–06/07 Date Comments 6/2007 Changed 8Y4 to 8Y7 package Revision history implemented 3/2007 Removed Pb product offering AT25128A_256A 23 ...
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