AT49LH002-33JC Atmel, AT49LH002-33JC Datasheet

IC FLASH 2MBIT 33MHZ 32PLCC

AT49LH002-33JC

Manufacturer Part Number
AT49LH002-33JC
Description
IC FLASH 2MBIT 33MHZ 32PLCC
Manufacturer
Atmel
Datasheet

Specifications of AT49LH002-33JC

Format - Memory
FLASH
Memory Type
FLASH
Memory Size
2M (256K x 8)
Speed
33MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 85°C
Package / Case
32-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT49LH002-33JC
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
AT49LH002-33JC SL383
Manufacturer:
Atmel
Quantity:
10 000
Features
Description
The AT49LH002 is a Flash memory device designed for use in PC and notebook BIOS
applications. The device complies with version 1.1 of Intel’s LPC Interface Specifica-
tion, providing support for both FWH and LPC memory read and write cycles. The
device can also automatically detect the memory cycle type to allow the AT49LH002
to be used as a FWH with Intel chipsets or as an LPC Flash with non-Intel chipsets.
Pin Configurations
Note:
Complies with Intel
Auto-detection of FWH and LPC Memory Cycles
Flexible, Optimized Sectoring for BIOS Applications
Two Configurable Interfaces
FWH/LPC Interface
A/A Mux Interface
Single Voltage Operation
Industry-Standard Package Options
– Supports both Firmware Hub (FWH) and LPC Memory Read and Write Cycles
– Can Be Used as FWH for Intel 8xx, E7xxx, and E8xxx Series Chipsets
– Can Be Used as LPC Flash for Non-Intel Chipsets
– 16-Kbyte Top Boot Sector, Two 8-Kbyte Sectors, One 32-Kbyte Sector,
– Or Memory Array Can Be Divided Into Four Uniform 64-Kbyte Sectors for Erasing
– FWH/LPC Interface for In-System Operation
– Address/Address Multiplexed (A/A Mux) Interface for Programming during
– Operates with the 33 MHz PCI Bus Clock
– 5-signal Communication Interface Supporting Byte Reads and Writes
– Two Hardware Write Protect Pins: TBL for Top Boot Sector and WP for All
– Five General-purpose Input (GPI) Pins for System Design Flexibility
– Identification (ID) Pins for Multiple Device Selection
– Sector Locking Registers for Individual Sector Read and Write Protection
– 11-pin Multiplexed Address and 8-pin Data Interface
– Facilitates Fast In-System or Out-of-System Programming
– 3.0V to 3.6V Supply Voltage for Read and Write Operations
– 32-lead PLCC
– 40-lead TSOP
[I/O0] FWH0/LAD0
Three 64-Kbyte Sectors
Manufacturing
Other Sectors
[ ] Designates A/A Mux Interface.
[A7] GPI1
[A6] GPI0
[A4] TBL
[A5] WP
[A3] ID3
[A2] ID2
[A1] ID1
[A0] ID0
5
6
7
8
9
10
11
12
13
PLCC
®
Low-Pin Count (LPC) Interface Specification Revision 1.1
29
28
27
26
25
24
23
22
21
IC [IC]
GND
NC
NC
VCC
INIT [OE]
FWH4/LFRAME [WE]
RES [RDY/BSY]
RES [I/O7]
[A10] GPI4
[RST] RST
[R/C] CLK
[A9] GPI3
[A8] GPI2
[A7] GPI1
[A6] GPI0
[A4] TBL
[A5] WP
[IC] IC
VCC
NC
NC
NC
NC
NC
NC
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
TSOP
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
GND
VCC
FWH4/LFRAME [WE]
INIT [OE]
RES [RDY/BSY]
RES [I/O7]
RES [I/O6]
RES [I/O5]
RES [I/O4]
VCC
GND
GND
FWH3/LAD3 [I/O3]
FWH2/LAD2 [I/O2]
FWH1/LAD1 [I/O1]
FWH0/LAD0 [I/O0]
ID0 [A0]
ID1 [A1]
ID2 [A2]
ID3 [A3]
Not Recommended
for New Design
Contact Atmel to discuss
the latest design in trends
and options
2-megabit
Firmware Hub
and Low-Pin
Count Flash
Memory
AT49LH002
3377B–FLASH–9/03
1

Related parts for AT49LH002-33JC

AT49LH002-33JC Summary of contents

Page 1

... TSOP Description The AT49LH002 is a Flash memory device designed for use in PC and notebook BIOS applications. The device complies with version 1.1 of Intel’s LPC Interface Specifica- tion, providing support for both FWH and LPC memory read and write cycles. The device can also automatically detect the memory cycle type to allow the AT49LH002 to be used as a FWH with Intel chipsets LPC Flash with non-Intel chipsets ...

Page 2

... BIOS routines to be developed and added while still main- taining the same overall device density. The memory array of the AT49LH002 can be sectored in two ways simply by using two differ- ent erase commands. Using one erase command allows the device to contain a total of seven sectors comprised of a 16-Kbyte boot sector, two 8-Kbyte sectors, a 32-Kbyte sector, and three 64-Kbyte sectors ...

Page 3

... When the device exits the reset state, it will default to the read array mode. 3377B–FLASH–9/03 Type Size (Bytes) 16K 8K 8K 32K 64K 64K 64K AT49LH002 Address Range 03C000H - 03FFFFH 03A000H - 03BFFFH 038000H - 039FFFH 030000H - 037FFFH 020000H - 02FFFFH 010000H - 01FFFFH 000000H - 00FFFFH Interface FWH/LPC A/A Mux ...

Page 4

... These pins are used as the A[10:6] pins in the A/A Mux interface. A[10:0] ADDRESS INPUTS: These pins are used for inputting the multiplexed address values when using the A/A Mux interface. The addresses are latched by the rising and falling edge of R/C pin. AT49LH002 4 Interface FWH/LPC A/A Mux ...

Page 5

... V These pins are used as the RDY/BSY and I/O[7:4] pins in the A/A Mux interface. 3377B–FLASH–9/03 voltages may produce spurious results and should not be CC and V requirements AT49LH002 Interface FWH/LPC A/A Mux X is less than ...

Page 6

... These field sequences are detailed in the FWH Interface Operation and LPC Interface Opera- tion sections. Since the AT49LH002 can be used as either a FWH Flash or an LPC Flash, the device is capable of automatically detecting which type of memory cycle is being performed. For a FWH/LPC cycle, the host will drive the FWH4/LFRAME pin low for one or more clock cycles to initiate the operation ...

Page 7

... GB addressable space if 16 FWH memory devices (256 MB each) were used in a system. The AT49LH002 only decodes the last six MADDR nibbles (A23 - A0) and ignores address bits A27 - A23 and A21 - A18. Address bit A22 is used to determine whether reads or writes to the device will be directed to the memory array (A22 = the register space (A22 = 0) ...

Page 8

... LPC bus back over to the master. Figure 2 shows a FWH read cycle that requires three SYNC clocks to access data from the memory array. AT49LH002 8 SYNC Type RSYNC (Ready SYNC) – Synchronization has been achieved with no error. ...

Page 9

... YYYY is the most significant nibble of the data byte. 1111b OUT then float The FWH memory device drives the bus to 1111b to indicate a turn-around cycle. Float then IN The FWH memory device floats its outputs, and the master regains control of the bus during this clock cycle. AT49LH002 ...

Page 10

... DATA 12 DATA 13 TAR0 14 TAR1 1111b (float) 15 RSYNC 0000b (ready) 16 TAR0 17 TAR1 1111b (float) Note: 1. Field contents are valid on the rising edge of the present clock cycle. AT49LH002 A15-A12 A11-A8 A7-A4 A3-A0 MADDR (1) FWH/LAD[3:0] Direction Comments 1110b IN FWH4/LFRAME must be active (low) for the device to respond. Only the last START field (before FWH4/LFRAME transitioning high) should be recognized ...

Page 11

... MADDR (MEMORY ADDRESS) FIELD: This is an 8-clock field that is used to provide a 32-bit (A31 - A0) memory address. The AT49LH002 only decodes the last six MADDR nibbles (A23 - A0) and ignores address bits A31 - A24 and A22 - A18. Address bit A23 is used to determine whether reads or writes to the device will be directed to the memory array (A23 = the register space (A23 = 0) ...

Page 12

... TAR field to the master to indicate that it is turning control of the LPC bus back over to the master. Figure 5 shows a LPC read cycle that requires three SYNC clocks to access data from the memory array. AT49LH002 12 SYNC Type RSYNC (Ready SYNC) – Synchronization has been achieved with no error. ...

Page 13

... YYYY is the most significant nibble of the data byte. 1111b OUT then float The LPC memory device drives the bus to 1111b to indicate a turn-around cycle. Float then IN The LPC memory device floats its outputs, and the master regains control of the bus during this clock cycle. AT49LH002 ...

Page 14

... MADDR 11 DATA 12 DATA 13 TAR0 14 TAR1 1111b (float) 15 RSYNC 0000b (ready) 16 TAR0 17 TAR1 1111b (float) Note: 1. Field contents are valid on the rising edge of the present clock cycle. AT49LH002 A27-A24 A23-A20 A19-A16 A15-A12 A11-A8 A7-A4 MADDR (1) FWH/LAD[3:0] Direction Comments 0000b IN FWH4/LFRAME must be active (low) for the device to respond ...

Page 15

... Table 5 and Table 9) and no internal Flash operation will be attempted. When the FWH4/LFRAME pin has been driven low to abort a cycle, the host may issue a START field of 1111b (stop/abort) to return the interface to the ready mode. 3377B–FLASH–9/03 AT49LH002 15 ...

Page 16

... WP pin is held low, program and standard Sector Erase command operations to sectors 5 through 0 will not be allowed. If using the Uniform Sector Erase command, then erase opera- tions to sectors 2, 1, and 0 cannot be performed, and erase protection for sectors 6 through 3 will be controlled by the TBL pin. AT49LH002 16 using the FWH/LPC interface and t PHFV ...

Page 17

... When returning from a reset condition or after power-up, the Sector Locking Registers will always default to a state of 01H. 3377B–FLASH–9/03 Hardware Write Protection For the Following Commands: Sector Erase (21H) Byte Program (40H or 10H) TBL AT49LH002 For the Following Command: Uniform Sector Erase (20H) TBL TBL TBL TBL ...

Page 18

... The Lock-Down bit is only cleared upon a device reset with RST or INIT or after a power-up. The current lock down status of a particular sector can be determined by reading the corresponding Lock-Down bit. AT49LH002 18 Register Memory Address Associated ...

Page 19

... RST or INIT signals) or power-cycled. Sector is not write-locked. Normal program and erase operations to the sector can occur. Sector is write-locked. Program and erase operations to the sector are prevented. This is the default state. Register Memory Address FWH Mode FFBC0100H AT49LH002 LPC Mode Register Type FF7C0100H Read Only 19 ...

Page 20

... The device will then enter standby mode when the FWH4/LFRAME pin is high and no internal operation is in progress. The FWH/LAD[3:0] pins will also be placed in a high- impedance state. Table 16. FWH Multiple Device Selection 0 (Boot Device) AT49LH002 20 Name Description Reserved Reserved for future use. ...

Page 21

... and V refer to the DC characteristics associated with the Flash memory output buffers min = 0.5V, V max = 0.8V Refer to Table 20 for Product ID addresses and data. ), the device outputs are enabled. Output pins I/O[7:0] are placed in an output-drive IL AT49LH002 OE WE Address ...

Page 22

... Either 40H or 10H is recognized by the device as the byte program command. 4. Following the Product ID Read command, read operations will access manufacturer and device ID information. Refer to Table 20 for Product ID addresses and data. AT49LH002 22 1st Command Cycle Type ...

Page 23

... CLEAR STATUS REGISTER: Error flags (SR[5,4,1]) in the Status Register can only be set to “1”s by the WSM and can only be reset by the Clear Status Register command. Therefore error is detected, the Status Register must be cleared before beginning another operation to avoid ambiguity. 3377B–FLASH–9/03 AT49LH002 23 ...

Page 24

... ID code. To exit the Product ID Read mode, any valid command can be written to the device. Table 20. Product ID Address and Data Code Manufacturer ID Device ID AT49LH002 24 Device is BUSY. A program or erase cycle is in progress. SR[6-1] values are invalid when SR[ Device is READY. The device is ready for any operation. ...

Page 25

... PCI output V and V spec AT49LH002 Stresses beyond those listed under “Absolute Maxi- mum Ratings” may cause permanent damage to the device. This is a stress rating only and functional oper- ation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied ...

Page 26

... I High Clamp Current CH slewr Output Rise Slew Rate slewf Output Fall Slew Rate Notes: 1. PCI specification output load is used (98.0 OUT (256 OUT CC AT49LH002 26 Conditions 0 < V < -500 µA OUT I = 1.5 mA OUT Condition ≤ 0 < V OUT CC 0.3 V < V < 0 OUT CC 0.7 V < ...

Page 27

... PCI components must work with any clock frequency between nominal DC and 33 MHz. Frequencies less than 16 MHz may be guaranteed by design rather than testing. 2. Applies only to rising edge of signal. Clock Waveform 3377B–FLASH–9/03 Condition peak-to-peak t CYC t HIGH 0 LOW 0 AT49LH002 Min Max Units ∞ V/ns 50 mV/ns 0.4 V CC, p-to-p (minimum) 27 ...

Page 28

... For purposes of Active/Float timing measurements, the high-Z or “off” state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 3. This parameter applies to any input type (excluding CLK). Output Timing Parameters (Valid Output Data) (Float Output Data) Input Timing Parameters FWH/LAD[3:0] (Valid Input Data) AT49LH002 28 (1) (2) (2) (3) (3) (2) CLK ...

Page 29

... V CC specifies the maximum peak-to-peak waveform allowed for measuring the input timing. Production PLPH (1) Typ 30 150 = +25° C and nominal voltages. A AT49LH002 Value V/ns and V . Timing parameters must be met with no more IH IL Min Max , this 100 CC ...

Page 30

... RST High to Row Address Setup PHAV Notes RST is asserted when the WSM is not busy (RDY/BSY = 1), the reset will complete within 100 ns reset recovery time, t PHAV AC Waveforms for Reset Operations V IH RDY/BSY RST ADDRESS V IL AT49LH002 30 Conditions max GND OUT min -2 min -100 µ ...

Page 31

... V IL 3377B–FLASH–9/03 (1)( after the rising edge of R/C without impact on t GLQV t AVAV Row Address Column Address Stable Stable t t CLAX AVCH t CHAX t CHQV High-Z t GLQX AT49LH002 Min Max 250 150 CHQV Next Address Stable t GLQV t GHQZ t QXGH Data Valid ...

Page 32

... V IH RDY/BSY RST V IL NOTES power-up and standby Write sector erase or program setup C = Write sector erase confirm or valid address and data D = Automated erase or program delay E = Read status register data F = Ready to write another command AT49LH002 32 ( AVCH t t CLAX CHAX t CHWH t t PHWL ...

Page 33

... Ordering Information I (mA) CC Active Standby 15 0.03 32J 32-lead, Plastic J-leaded Chip Carrier Package (PLCC) 40T 40-lead, Thin Small Outline Package (TSOP) 3377B–FLASH–9/03 Ordering Code AT49LH002-33JC AT49LH002-33TC Package Type AT49LH002 Package Operation Range 32J Extended Commercial 40T (0° to 85° ...

Page 34

... Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum. 2325 Orchard Parkway San Jose, CA 95131 R AT49LH002 34 1.14(0.045) X 45˚ PIN NO. 1 IDENTIFIER E1 E ...

Page 35

... Lead coplanarity is 0.10 mm maximum. 2325 Orchard Parkway San Jose, CA 95131 R 3377B–FLASH–9/03 PIN SEATING PLANE A1 TITLE 40T, 40-lead ( Package) Plastic Thin Small Outline Package, Type I (TSOP) AT49LH002 0º ~ 8º GAGE PLANE COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM MAX SYMBOL A – – ...

Page 36

... No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems. ...

Related keywords