AT45DB041B-CNU Atmel, AT45DB041B-CNU Datasheet

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AT45DB041B-CNU

Manufacturer Part Number
AT45DB041B-CNU
Description
IC FLASH 4MBIT 20MHZ 8CASON
Manufacturer
Atmel
Datasheet

Specifications of AT45DB041B-CNU

Format - Memory
FLASH
Memory Type
DataFLASH
Memory Size
4M (2048 pages x 264 bytes)
Speed
20MHz
Interface
SPI, 3-Wire Serial
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-CASON
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
1. Description
The AT45DB041B is an SPI compatible serial interface Flash memory ideally suited
for a wide variety of digital voice-, image-, program code- and data-storage applica-
tions. Its 4,325,376 bits of memory are organized as 2048 pages of 264 bytes each. In
addition to the main memory, the AT45DB041B also contains two SRAM data buffers
of 264 bytes each.
The buffers allow receiving of data while a page in the main memory is being repro-
grammed, as well as reading or writing a continuous data stream. EEPROM emulation
(bit or byte alterability) is easily handled with a self-contained three step Read-Modify-
Write operation. Unlike conventional Flash memories that are accessed randomly with
multiple address lines and a parallel interface, the DataFlash uses a SPI serial inter-
face to sequentially access its data. DataFlash supports SPI mode 0 and mode 3. The
simple serial interface facilitates hardware layout, increases system reliability, mini-
mizes switching noise, and reduces package size and active pin count. The device is
optimized for use in many commercial and industrial applications where high density,
low pin count, low voltage, and low power are essential. The device operates at clock
frequencies up to 20 MHz with a typical active read current consumption of 4 mA.
To allow for simple in-system reprogrammability, the AT45DB041B does not require
high input voltages for programming. The device operates from a single power supply,
2.5V to 3.6V or 2.7V to 3.6V, for both the program and read operations. The
AT45DB041B is enabled through the chip select pin (CS) and accessed via a three-
wire interface consisting of the Serial Input (SI), Serial Output (SO), and the Serial
Clock (SCK).
All programming cycles are self-timed, and no separate erase cycle is required before
programming.
Single 2.5V - 3.6V or 2.7V - 3.6V Supply
Serial Peripheral Interface (SPI) Compatible
20 MHz Max Clock Frequency
Page Program Operation
Supports Page and Block Erase Operations
Two 264-byte SRAM Data Buffers – Allows Receiving of Data
while Reprogramming the Flash Memory Array
Continuous Read Capability through Entire Array
Low Power Dissipation
Hardware Data Protection Feature
5.0V-tolerant Inputs: SI, SCK, CS, RESET, and WP Pins
Commercial and Industrial Temperature Ranges
Green (Pb/Halide-free/RoHS Compliant) Package Options
– Single Cycle Reprogram (Erase and Program)
– 2048 Pages (264 Bytes/Page) Main Memory
– Ideal for Code Shadowing Applications
– 4 mA Active Read Current Typical
– 2 µA CMOS Standby Current Typical
4-megabit
2.5-volt or
2.7-volt
DataFlash
AT45DB041B
For New
Designs Use
AT45DB041D
3443D–DFLSH–2/08
®

Related parts for AT45DB041B-CNU

AT45DB041B-CNU Summary of contents

Page 1

... The device operates from a single power supply, 2.5V to 3.6V or 2.7V to 3.6V, for both the program and read operations. The AT45DB041B is enabled through the chip select pin (CS) and accessed via a three- wire interface consisting of the Serial Input (SI), Serial Output (SO), and the Serial Clock (SCK) ...

Page 2

... Pin Configurations and Packages Table 2-1. Pin Name CS SCK RESET RDY/BUSY Figure 2-1. Figure 2-2. Figure 2-4. Note: AT45DB041B 2 Pin Configurations Function Chip Select Serial Clock Serial Input Serial Output Hardware Page Write Protect Pin Chip Reset Ready/Busy TSOP Top View Type 1 RDY/BUSY 1 ...

Page 3

... RDY/BUSY 4. Memory Array To provide optimal flexibility, the memory array of the AT45DB041B is divided into three levels of granularity comprising of sectors, blocks, and pages. The Memory Architecture Diagram illus- trates the breakdown of each level and details the number of pages per sector and block. All program operations to the DataFlash occur on a page-by-page basis ...

Page 4

... When the last bit in the main memory array has been read, the device will continue reading back at the beginning of the first page of memory. As with crossing over page boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the array. AT45DB041B 4 Table 5-3 on page 10 3443D–DFLSH–2/08 ...

Page 5

... CS remains low and SCK is being toggled) starting again with bit 7. The data in the status register is constantly updated, so each repeating sequence will output new data. Table 5-1. RDY/BUSY 3443D–DFLSH–2/08 Status Register Format Bit 7 Bit 6 Bit 5 COMP 0 AT45DB041B Bit 4 Bit 3 Bit 2 Bit CAR Bit ...

Page 6

... The device density is indicated using bits and 2 of the status register. For the AT45DB041B, the four bits are and 1. The decimal value of these four binary bits does not equate to the device density; the four bits represent a combinational code relating to differing densities of Serial DataFlash devices, allowing a total of sixteen different density configurations ...

Page 7

... During this time, the status register will indicate that the part is busy. BE PA7 PA6 PA5 PA4 • • • • • • • • • • • • AT45DB041B PA3 PA2 PA1 PA0 • • • • • • • • • • • • Dur- ...

Page 8

... The operation is internally self-timed and should AT45DB041B 8 ), the status register will indicate that the part is busy. On completion of the com- ...

Page 9

... See application note AN-4 (“Using Atmel’s Serial DataFlash”) for more details. 3443D–DFLSH–2/08 . During this time, the status register will indicate that the EP Figure 17-1 on page 27 Figure 17-2 on page 28 is recommended. Each page within a sector must be AT45DB041B is recommended. Otherwise, if multiple bytes ...

Page 10

... Auto Page Rewrite through Buffer 2 Note: In Tables 2 and 3, an SCK mode designation of “Any” denotes any one of the four modes of operation (Inactive Clock Polarity Low, Inactive Clock Polarity High, SPI Mode 0, or SPI Mode 3). AT45DB041B 10 SCK Mode Inactive Clock Polarity Low or High ...

Page 11

... The busy status indicates that the Flash memory array and one of the buffers cannot be accessed; read and write operations to the other buffer can still be performed. 3443D–DFLSH–2/08 AT45DB041B 11 ...

Page 12

... D2H D4H D6H D7H E8H Note Reserved Bit P = Page Address Bit B = Byte/Buffer Address Bit x = Don’t Care AT45DB041B the minimum datasheet value, the system should wait Address Byte Address Byte N/A ...

Page 13

... Output High Voltage OH Note during a buffer read is 20mA maximum. cc1 3443D–DFLSH–2/08 *NOTICE: + 0.6V CC AT45DB041B (2.5V Version) 0° 70° C – 2. the minimum specified datasheet value, the system should wait 20 ms before an opera- CC Condition CS, RESET all inputs CC at CMOS levels MHz ...

Page 14

... Input Test Waveforms and Measurement Levels < (10 10.2 Output Test Load AT45DB041B 14 2. 2.0 DRIVING MEASUREMENT 0.8 LEVELS LEVEL 0.45V DEVICE UNDER TEST 30 pF AT45DB041B (2.5V Version) AT45DB041B Min Max Min Max 250 250 250 250 250 250 200 200 ...

Page 15

... HIGH IMPEDANCE SO SI Note: The CS signal should be in the high state before the RESET signal is deasserted. 3443D–DFLSH–2/ CSS VALID OUT VALID CSS VALID OUT VALID IN AT45DB041B CSH t HO DIS HIGH IMPEDANCE CSH t DIS HIGH IMPEDANCE t REC t CSS t RST HIGH IMPEDANCE 15 ...

Page 16

... It is recommended that “r” logical “0” for densities of 4M bits or smaller. 3. For densities larger than 4M bits, the “r” bits become the most significant Page Address bit for the appropriate density. AT45DB041B 16 SI ...

Page 17

... PA10-7 PA6-0, BFA8 BFA7-0 X X···X, BFA8 BFA7-0 Starts self-timed erase/program operation CMD PA10-7 PA6-0, X AT45DB041B BUFFER 2 TO PAGE PROGRAM BUFFER 2 (256 BYTES) BUFFER 2 WRITE · Completes writing into selected buffer · Starts self-timed erase/program operation n n+1 Last Byte · ...

Page 18

... Main Memory Page to Buffer Transfer (Data from Flash Page Read into Buffer 13.3 Buffer Read Each transition represents 8 bits and 8 clock cycles AT45DB041B 18 FLASH MEMORY ARRAY MAIN MEMORY PAGE READ I/O INTERFACE SO PA6-0, BA8 BA7-0 X Starts reading page data into buffer ...

Page 19

... HIGH-IMPEDANCE SO 14.2 Main Memory Page Read (Opcode: 52H) CS SCK COMMAND OPCODE 14.3 Buffer Read (Opcode: 54H or 56H) CS SCK COMMAND OPCODE 3443D–DFLSH–2/ DATA OUT HIGH-IMPEDANCE HIGH-IMPEDANCE AT45DB041B LSB MSB BIT 2111 BIT PAGE n PAGE n DATA OUT MSB DATA OUT MSB ...

Page 20

... Status Register Read (Opcode: 57H) CS SCK COMMAND OPCODE HIGH-IMPEDANCE SO AT45DB041B STATUS REGISTER OUTPUT MSB LSB MSB 3443D–DFLSH–2/08 ...

Page 21

... HIGH-IMPEDANCE SO 15.2 Main Memory Page Read (Opcode: 52H) CS SCK COMMAND OPCODE 15.3 Buffer Read (Opcode: 54H or 56H) CS SCK COMMAND OPCODE 3443D–DFLSH–2/ DATA OUT HIGH-IMPEDANCE HIGH-IMPEDANCE AT45DB041B LSB MSB BIT 2111 BIT PAGE n PAGE n DATA OUT MSB DATA OUT MSB ...

Page 22

... Status Register Read (Opcode: 57H) CS SCK COMMAND OPCODE HIGH-IMPEDANCE SO AT45DB041B STATUS REGISTER OUTPUT MSB LSB MSB 3443D–DFLSH–2/08 ...

Page 23

... HIGH-IMPEDANCE SO 16.2 Main Memory Page Read (Opcode: D2H) CS SCK COMMAND OPCODE 16.3 Buffer Read (Opcode: D4H or D6H) CS SCK COMMAND OPCODE 3443D–DFLSH–2/ DATA OUT HIGH-IMPEDANCE HIGH-IMPEDANCE AT45DB041B LSB MSB BIT 2111 BIT PAGE n PAGE n DATA OUT MSB DATA OUT MSB ...

Page 24

... Status Register Read (Opcode: D7H) CS SCK COMMAND OPCODE HIGH-IMPEDANCE SO AT45DB041B MSB STATUS REGISTER OUTPUT LSB 3443D–DFLSH–2/ MSB ...

Page 25

... HIGH-IMPEDANCE SO 17.2 Main Memory Page Read (Opcode: D2H) CS SCK COMMAND OPCODE 17.3 Buffer Read (Opcode: D4H or D6H) CS SCK COMMAND OPCODE 3443D–DFLSH–2/ DATA OUT HIGH-IMPEDANCE HIGH-IMPEDANCE AT45DB041B LSB MSB BIT 2111 BIT PAGE n PAGE n DATA OUT MSB DATA OUT MSB ...

Page 26

... Status Register Read (Opcode: D7H) CS SCK COMMAND OPCODE HIGH-IMPEDANCE SO AT45DB041B STATUS REGISTER OUTPUT MSB LSB MSB 3443D–DFLSH–2/08 ...

Page 27

... The algorithm above shows the programming of a single page. The algorithm will be repeated sequentially for each page within the entire array. 3443D–DFLSH–2/08 START provide address and data THROUGH BUFFER (82H, 85H) END AT45DB041B BUFFER WRITE (84H, 87H) BUFFER TO MAIN MEMORY PAGE PROGRAM (83H, 86H) 27 ...

Page 28

... Table 17-1. Sector Addressing PA10 PA9 PA8 AT45DB041B 28 START provide address of page to modify MAIN MEMORY PAGE TO BUFFER TRANSFER (53H, 55H) BUFFER WRITE (82H, 85H) BUFFER TO MAIN MEMORY PAGE PROGRAM (2) AUTO PAGE REWRITE (58H, 59H) INCREMENT PAGE (2) ADDRESS POINTER END PA7 PA6 PA5 0 ...

Page 29

... Ordering Code AT45DB041B-CC AT45DB041B-CNC AT45DB041B-RC AT45DB041B-SC AT45DB041B-TC AT45DB041B-CI AT45DB041B-CNI AT45DB041B-RI AT45DB041B-SI AT45DB041B-TI AT45DB041B-RC-2.5 AT45DB041B-CNC-2.5 AT45DB041B-SC-2.5 AT45DB041B-TC-2.5 Ordering Code AT45DB041B-CU AT45DB041B-CNU AT45DB041B-RU AT45DB041B-SU AT45DB041B-TU Package Type AT45DB041B Package Operation Range 14C1 8CN3 Commercial (1) 28R (0° 70° C) 2.7V to 3.6V 8S2 28T 14C1 ...

Page 30

... Packaging Information 19.1 14C1 – CBGA Dimensions in Millimeters and (Inches). Controlling dimension: Millimeters. 1.25 (0.049) REF 1.00 (0.0394) BSC NON-ACCUMULATIVE NON-ACCUMULATIVE 2325 Orchard Parkway San Jose, CA 95131 R AT45DB041B 30 4.60(0.181) 4.40(0.173 7.10(0.280) 6.90(0.272) TOP VIEW 1.40 (0.055) MAX 2.0 (0.079) 1.50 (0.059) REF 3 ...

Page 31

... D Top View Side View Pin1 Pad Corner Bottom View TITLE 8CN3, 8-pad ( 1.0 mm Body), Lead Pitch 1.27 mm, Chip Array Small Outline No Lead Package (CASON) AT45DB041B A A1 COMMON DIMENSIONS (Unit of Measure = mm) MIN MAX SYMBOL NOM A 1.0 A1 0.17 0.21 0.25 b ...

Page 32

... Note: 1. Dimensions D and E1 do not include mold Flash or protrusion. Mold Flash or protrusion shall not exceed 0.25 mm (0.010"). 2325 Orchard Parkway San Jose, CA 95131 R Note: 1. The next generation DataFlash devices will not be offered in 28-SOIC package, therefore, this package is not recommended for new designs. AT45DB041B TITLE 28R, 28-lead, 0.330" ...

Page 33

... San Jose, CA 95131 R 3443D–DFLSH–2/ TOP VIEW TOP VIEW SIDE VIEW SIDE VIEW TITLE 8S2, 8-lead, 0.209" Body, Plastic Small Outline Package (EIAJ) AT45DB041B θ θ END VIEW END VIEW COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM MAX SYMBOL A 1.70 2.16 A1 0.05 ...

Page 34

... E Notes: 1. This package conforms to JEDEC reference MO-183. 2. Dimensions D1 and E do not include mold protrusion. Allowable protrusion 0.15 mm per side and 0.25 mm per side. 3. Lead coplanarity is 0.10 mm maximum. 2325 Orchard Parkway San Jose, CA 95131 R AT45DB041B 34 PIN SEATING PLANE A1 TITLE 28T, 28-lead (8 x 13.4 mm) Plastic Thin Small Outline Package, Type I (TSOP) 0º ...

Page 35

... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...

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