AT45DB081D-SSU-2.5 Atmel, AT45DB081D-SSU-2.5 Datasheet

IC FLASH 8MBIT 50MHZ 8SOIC

AT45DB081D-SSU-2.5

Manufacturer Part Number
AT45DB081D-SSU-2.5
Description
IC FLASH 8MBIT 50MHZ 8SOIC
Manufacturer
Atmel
Datasheet

Specifications of AT45DB081D-SSU-2.5

Format - Memory
FLASH
Memory Type
DataFLASH
Memory Size
8M (4096 pages x 264 bytes)
Speed
50MHz
Interface
SPI, RapidS
Voltage - Supply
2.5 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (3.9mm Width)
Architecture
Sectored
Interface Type
SPI
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.5 V
Maximum Operating Current
15 mA
Mounting Style
SMD/SMT
Organization
64 KB x 16
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT45DB081D-SSU-2.5
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Features
1. Description
The Atmel
ideally suited for a wide variety of digital voice-, image-, program code- and data-stor-
age applications. The AT45DB081D supports Atmel RapidS
applications requiring very high speed operations. RapidS serial interface is SPI com-
patible for frequencies up to 66MHz. Its 8,650,752-bits of memory are organized as
4,096 pages of 256-bytes or 264-bytes each. In addition to the main memory, the
AT45DB081D also contains two SRAM buffers of 256-/264-bytes each. The buffers
allow the receiving of data while a page in the main Memory is being reprogrammed,
as well as writing a continuous data stream. EEPROM emulation (bit or byte alterabil-
ity) is easily handled with a self-contained three step read-modify-write operation.
Unlike conventional Flash memories that are accessed randomly with multiple
Single 2.5V or 2.7V to 3.6V Supply
RapidS Serial Interface: 66MHz Maximum Clock Frequency
User Configurable Page Size
Page Program Operation
Flexible Erase Options
Two SRAM Data Buffers (256-/264-Bytes)
Continuous Read Capability through Entire Array
Low-power Dissipation
Hardware and Software Data Protection Features
Sector Lockdown for Secure Code and Data Storage
Security: 128-byte Security Register
JEDEC Standard Manufacturer and Device ID Read
100,000 Program/Erase Cycles Per Page Minimum
Data Retention – 20 Years
Industrial Temperature Range
Green (Pb/Halide-free/RoHS Compliant) Packaging Options
– SPI Compatible Modes 0 and 3
– 256-Bytes per Page
– 264-Bytes per Page
– Page Size Can Be Factory Pre-configured for 256-Bytes
– Intelligent Programming Operation
– 4,096 Pages (256/264-Bytes/Page) Main Memory
– Page Erase (256-Bytes)
– Block Erase (2-Kbytes)
– Sector Erase (64-Kbytes)
– Chip Erase (8Mbits)
– Allows Receiving of Data while Reprogramming the Flash Array
– Ideal for Code Shadowing Applications
– 7mA Active Read Current Typical
– 25µA Standby Current Typical
– 15µA Deep Power Down Typical
– Individual Sector
– Individual Sector
– 64-byte User Programmable Space
– Unique 64-byte Device Identifier
®
AT45DB081D is a 2.5V or 2.7V, serial-interface Flash memory
serial interface for
8-megabit
2.5V or 2.7V
Atmel DataFlash
Atmel AT45DB081D
Atmel RapidS
3596M–DFLASH–5/10

Related parts for AT45DB081D-SSU-2.5

AT45DB081D-SSU-2.5 Summary of contents

Page 1

... Its 8,650,752-bits of memory are organized as 4,096 pages of 256-bytes or 264-bytes each. In addition to the main memory, the AT45DB081D also contains two SRAM buffers of 256-/264-bytes each. The buffers allow the receiving of data while a page in the main Memory is being reprogrammed, as well as writing a continuous data stream ...

Page 2

... To allow for simple in-system reprogrammability, the Atmel AT45DB081D does not require high input voltages for programming. The device operates from a single power supply, 2.5V to 3.6V or 2.7V to 3.6V, for both the program and read operations. The AT45DB081D is enabled through the chip select pin (CS) and accessed via a three-wire interface consisting of the Serial Input (SI), Serial Output (SO), and the Serial Clock (SCK) ...

Page 3

... Ground: The ground reference for the power supply. GND should be connected to the system GND ground. 3596M–DFLASH–5/10 pin is used to supply the source voltage to the device. CC voltages may produce spurious results and should not be attempted. CC Atmel AT45DB081D Asserted State Type Low Input – Input – ...

Page 4

... SECTOR 2 = 256 Pages 65,536-/67,584-bytes SECTOR 14 = 256 Pages 65,536-/67,584-bytes SECTOR 15 = 256 Pages 65,536-/67,584-bytes Atmel AT45DB081D 4 FLASH MEMORY ARRAY I/O INTERFACE SI ® AT45DB081D is divided into three levels of granularity com- BLOCK ARCHITECTURE SECTOR 0a BLOCK 0 BLOCK 1 BLOCK 2 BLOCK 30 BLOCK 31 BLOCK 32 BLOCK 33 BLOCK 62 BLOCK 63 ...

Page 5

... The CS pin must remain low during the loading of the opcode, the address bytes, the don’t care bytes, and the reading of data. When the end of a page in main memory is reached during a 3596M–DFLASH–5/10 Atmel AT45DB081D Table 15-1 on page 27 ® ® ...

Page 6

... When the end of a page in the main memory is reached during a Continuous Array Read, the device will continue reading at the beginning of the next page with no delays incurred Atmel AT45DB081D 6 specification. The Continuous Array Read bypasses both data buffers and leaves the specification ...

Page 7

... A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin (SO). 3596M–DFLASH–5/10 specification. The Main Memory Page Read bypasses both data buffers and SCK . The D1H and D3H opcode can be used for lower frequency CAR1 Atmel AT45DB081D ® ® DataFlash standard page size (264-bytes), . CAR2 ...

Page 8

... Erase or Block Erase). The programming of the page is internally self-timed and should take place in a maximum time of t During this time, the status register will indicate that the part is busy. Atmel AT45DB081D 8 ® ...

Page 9

... BE PA7/ PA6/ PA5/ PA4/ A15 A14 A13 A12 • • • • • • • • • • • • Atmel AT45DB081D PA3/ PA2/ PA1/ PA0/ A11 A10 • • • • • • • • • • • • Block ...

Page 10

... The erase operation is internally self-timed and should take place in a time of t The Chip Erase command will not affect sectors that are protected or locked down; the contents of those sectors will remain unchanged. Only those sectors that are not protected or locked down will be erased. Atmel AT45DB081D 10 ® ® DataFlash ...

Page 11

... Status Register. 3596M–DFLASH–5/10 Chip Erase Command Chip Erase CS Opcode SI Byte 1 Each transition represents 8 bits Refer to errata regarding Chip Erase on Atmel AT45DB081D Byte 1 Byte 2 Byte 3 C7H 94H 80H Opcode Opcode Opcode Byte 2 Byte 3 ...

Page 12

... Software controlled protection is useful in applications in which the WP pin is not or cannot be controlled by a host processor. In such instances, the WP pin may be left floating (the WP pin is internally pulled high) and sector protection can be controlled using the Enable Sector Protection and Disable Sector Protection commands. Atmel AT45DB081D 12 Enable Sector Protection Command Byte 1 ...

Page 13

... WPE 2 Disable Sector Command Protection Command – Issue Command Issue Command X Not Issued Yet or 2 Issue Command – Issue Command Atmel AT45DB081D , then the content of the Sector CC time) as long as the Enable Sec- WPD 3 Sector Protection Status X Disabled Disabled – Enabled X Enabled ...

Page 14

... If for some reason an erroneous program or erase com- mand is sent to the device immediately after erasing the Sector Protection Register and before the register can be reprogrammed, then the erroneous program or erase command will not be processed because all sectors would be protected. Atmel AT45DB081D 14 Sector Protection Register Sector 0 (0a, 0b) ...

Page 15

... Erase Sector Protection Register CS Opcode Opcode SI Byte 1 Byte 2 Each transition represents 8 bits , during which time the Status Register will indicate that the device is busy Atmel AT45DB081D Byte 2 Byte 3 Byte 4 2AH 7FH Opcode Opcode Byte 3 Byte 4 Section 9.1, the Sector Protection Reg- ...

Page 16

... Sector Protection Register is reprogrammed), then the application will need to limit this practice. Instead, a combination of temporarily unprotecting individual sectors along with dis- abling sector protection completely will need to be implemented by the application to ensure that the limit of 10,000 cycles is not exceeded. Atmel AT45DB081D 16 Program Sector Protection Register Command Opcode ...

Page 17

... Figure 10-1. Sector Lockdown CS Opcode SI Byte 1 Each transition represents 8 bits 3596M–DFLASH–5/10 Sector Lockdown Byte 1 3DH Opcode Opcode Opcode Address Byte 2 Byte 3 Byte 4 Atmel AT45DB081D , during which time the Status P Byte 2 Byte 3 2AH 7FH Address Address Bytes Bytes Bytes Byte 4 30H 17 ...

Page 18

... Read Sector Lockdown Register Note: Figure 10-2. Read Sector Lockdown Register CS SI Opcode SO Each transition represents 8 bits Atmel AT45DB081D 18 Sector Lockdown Register Sector 0 (0a, 0b) (Page 0-7) Bit 7, 6 details the values read from the Sector Lockdown Register. Sector Lockdown Register xx = Dummy Byte ...

Page 19

... Status Register will indicate that the device is busy. If the device P Opcode Opcode Opcode Data Byte Byte 2 Byte 3 Byte 4 Atmel AT45DB081D ® and will contain a unique Security Register Byte Number  Factory Programmed by Atmel ...

Page 20

... The CS pin must be low while toggling the SCK pin to load the opcode and the address bytes from the input pin (SI). On the low-to-high transition of the CS pin, the data bytes in the selected main memory page will be compared with the data bytes in buffer 1 or buffer 2. During this time (t Atmel AT45DB081D ...

Page 21

... DataFlash . During this time, the status register will indicate that the part is busy. EP Figure 25-1 (page 45) is recommended. Otherwise, if multiple bytes in a Figure 25-2 (page 46) is recommended. Each page within a sector must be Atmel AT45DB081D standard page size (264-bytes), a 1-byte opcode, 21 ...

Page 22

... The device density is indicated using bits five, four, three, and two of the status register. For the Atmel AT45DB081D, the four bits are 1001 The decimal value of these four binary bits does not equate to the device density; the four bits represent a combinational code relating to differing densities of DataFlash devices ...

Page 23

... Resume from Deep Power-down CS SI Each transition represents 8 bits ® ® DataFlash standard page size (264-bytes). The “power of 2” page size is a Atmel AT45DB081D time. The CS pin must remain high during RDPD Opcode ABH Opcode Section 26. ”Ordering Information” on Section 13.1). ...

Page 24

... Deasserting the CS pin will terminate the Manufacturer and Device ID Read operation and put the SO pin into a high-impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data be read. Atmel AT45DB081D 24 , during which time the Status Register will indicate that the device is ...

Page 25

... Device ID Device ID Extended Byte n Byte 1 Byte 2 Device Information String Length Each transition represents 8 bits Atmel AT45DB081D Manufacturer ID Family Code 001 = Atmel DataFlash Density Code 00101 = 8-Mbit MLC Code 000 = 1-bit/Cell Technology Product Version 00000 = Initial Version Byte Count 00H = 0 Bytes of Information ...

Page 26

... Group C can be executed. The Group B commands using buffer 1 should use Group C commands using buffer 2 and vice versa. Finally, during the internally self- timed portion of a Group D command, only the Status Register Read command should be executed. Atmel AT45DB081D 26 3596M–DFLASH–5/10 ...

Page 27

... Disable Sector Protection Erase Sector Protection Register Program Sector Protection Register Read Sector Protection Register Sector Lockdown 3596M–DFLASH–5/10 Read Commands Program and Erase Commands Protection and Security Commands Atmel AT45DB081D Opcode D2H E8H 03H 0BH D1H D3H D4H D6H ...

Page 28

... Manufacturer and Device ID Read Table 15-5. Command Buffer 1 Read Buffer 2 Read Main Memory Page Read Continuous Array Read Status Register Read Note: Atmel AT45DB081D 28 Protection and Security Commands Additional Commands (1) Legacy Commands 1. These legacy commands are not recommended for new designs Opcode 35H ...

Page 29

... Address Byte Address Byte N/A N/A N/A N/A N/A N N/A N Atmel AT45DB081D Address Byte N/A N Additional Don’t Care Bytes N N/A A N N N/A N/A N/A N/A A ...

Page 30

... B9h ABh D1h D2h D3h D4h D6h D7h E8h Notes Page Address Bit B = Byte/Buffer Address Bit Atmel AT45DB081D 30 Address Byte Address Byte N/A N/A N/A N/A N/A N ...

Page 31

... Chip Select low CC Power-Up Device Delay before Write Allowed Power-ON Reset Voltage ® ™ RapidS serial interface is controlled by the clock SCK, serial input SI and chip Atmel AT45DB081D ). At this time, all POR (min.), the t delay is required CC VCSL rises above the Power-on Reset threshold ...

Page 32

... After power is applied and V tional mode is started Atmel AT45DB081D 32 *NOTICE: + 0.6V CC Atmel AT45DB081D (2.5V Version) Ind. -40C to 85C 2. the minimum specified datasheet value, the system should wait 10 ms before an opera- CC Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam- age to the device. The " ...

Page 33

... CS, RESET all IH inputs at CMOS levels f = 20MHz 0mA; OUT 33MHz 0mA; OUT 50MHz 0mA; OUT 66MHz 0mA; OUT CMOS levels CMOS levels I 1.6mA 2. -100µ Atmel AT45DB081D Min Typ Max 0 0.7 0.4 - 0.2V Units µA µ µA µ ...

Page 34

... PE t Block Erase Time (2,048-/2,112-bytes Sector Erase Time (65,536/67,584 Chip Erase Time CE t RESET Pulse Width RST t RESET Recovery Time REC Atmel AT45DB081D 34 Atmel AT45DB081D (2.5V Version) Atmel AT45DB081D Min Typ Max Min 6.8 6.8 6.8 6.8 0.1 0.1 0.1 0 ...

Page 35

... UNDER TEST ™ RapidS serial interface but for frequencies up to 66MHz. Waveforms 1 and 2 are com- period. These timing waveforms are valid over the full frequency range (max- WL Atmel AT45DB081D AC MEASUREMENT LEVEL 30pF page 36. Waveform 1 shows the SCK signal being ). Timing waveforms 1 and 2 conform to ...

Page 36

... HIGH IMPEDANCE SO SI 21.2 Waveform 2 – SPI Mode 3 Compatible (for Frequencies up to 66MHz) CS SCK HIGH 21.3 Waveform 3 – Atmel RapidS Mode SCK HIGH IMPEDANCE SO SI 21.4 Waveform 4 – Atmel RapidS Mode SCK HIGH Atmel AT45DB081D CSS VALID OUT VALID CSS WL WH ...

Page 37

... H. Slave clocks out second bit of BYTE-SO I. Master clocks in last bit of BYTE-SO 3596M–DFLASH–5/10 ® ™ RapidS function's ability to operate at higher clock frequen- ® is designed to always clock its data out on the falling edge of the SCK signal LSB BYTE-MOSI F Atmel AT45DB081D MSB BYTE- LSB 37 ...

Page 38

... Command Sequence for Read/Write Operations for Page Size 256-Bytes (Except Status Register Read, Manufacturer and Device ID Read) SI (INPUT) MSB 21.8 Command Sequence for Read/Write Operations for Page Size 264-Bytes (Except Status Register Read, Manufacturer and Device ID Read) SI (INPUT) MSB Atmel AT45DB081D 38 CMD 8 bits 8 bits Don’t Care Page Address ...

Page 39

... DON'T CARE + BFA7-BFA0 n X BFA7-0 X···X, BFA8 Starts self-timed erase/program operation BINARY PAGE SIZE A19- DON'T CARE BITS CMD PA10-7 PA6, X Atmel AT45DB081D Completes writing into selected buffer n+1 Last Byte XXXX 1st byte read n+1 = 2nd byte read 39 ...

Page 40

... Main Memory Page Read CS SI (INPUT) CMD SO (OUTPUT) 23.2 Main Memory Page to Buffer Transfer (Data from Flash Page Read into Buffer (INPUT) SO (OUTPUT) Atmel AT45DB081D 40 FLASH MEMORY ARRAY MAIN MEMORY READ PAGE READ I/O INTERFACE SO ADDRESS FOR BINARY PAGE SIZE A15-A8 ...

Page 41

... SO 3596M–DFLASH–5/10 BINARY PAGE SIZE 15 DON'T CARE + BFA8-BFA0 CMD X X..X, BFA9 ADDRESS BITS 32 DON'T CARE BITS MSB MSB ADDRESS BITS A19 - MSB MSB Atmel AT45DB081D 1 Dummy Byte BFA7 DATA BYTE MSB BIT 2047/2111 OF PAGE DON'T CARE DATA BYTE MSB n+1 ...

Page 42

... Continuous Array Read (Low Frequency: Opcode 03H SCK MSB HIGH-IMPEDANCE SO 24.4 Main Memory Page Read (Opcode: D2H SCK OPCODE MSB HIGH-IMPEDANCE SO 24.5 Buffer Read (Opcode D4H or D6H SCK OPCODE MSB HIGH-IMPEDANCE SO Atmel AT45DB081D OPCODE ADDRESS BITS A19- MSB ADDRESS BITS 32 DON'T CARE BITS MSB MSB 6 7 ...

Page 43

... ADDRESS BITS BINARY PAGE SIZE = 16 DON'T CARE + BFA7-BFA0 STANDARD ATMEL DATAFLASH PAGE SIZE = OPCODE 15 DON'T CARE + BFA8-BFA0 MSB OPCODE DON'T CARE MSB OPCODE DON'T CARE MSB Atmel AT45DB081D DATA BYTE MSB MSB DATA BYTE MSB MSB DATA BYTE MSB MSB 43 ...

Page 44

... Read Security Register (Opcode 77H SCK MSB HIGH-IMPEDANCE SO 24.10 Status Register Read (Opcode D7H SCK SI 1 MSB HIGH-IMPEDANCE SO 24.11 Manufacturer and Device Read (Opcode 9FH) CS SCK SI HIGH-IMPEDANCE SO Note: Each transition Atmel AT45DB081D OPCODE DON'T CARE MSB OPCODE STATUS REGISTER DATA ...

Page 45

... The algorithm above shows the programming of a single page. The algorithm will be repeated sequentially for each page within the entire array. 3596M–DFLASH–5/10 START provide address (82H, 85H) END Atmel AT45DB081D and data BUFFER WRITE (84H, 87H) BUFFER TO MAIN MEMORY PAGE PROGRAM (83H, 86H) ...

Page 46

... Other algorithms can be used to rewrite portions of the Flash array. Low-power applications may choose to wait until 10,000 cumulative page erase and program operations have accumulated before rewriting all pages of the sector. See application note AN-4 (“Using Atmel Serial DataFlash”) for more details. Atmel AT45DB081D 46 START ...

Page 47

... AT45DB081D-SU (3) AT45DB081D-SU-SL954 (4) AT45DB081D-SU-SL955 AT45DB081D-MU-2.5 AT45DB081D-SSU-2.5 AT45DB081D-SU-2.5 Notes: 1. The shipping carrier option is not marked on the devices. 2. Standard parts are shipped with the page size set to 264-bytes. The user is able to configure these parts to a 256-byte page size if desired. 3. Parts ordered with suffix SL954 are shipped in bulk with the page size set to 256-bytes. Parts will have a 954 or SL954 marked on them ...

Page 48

... Packaging Information 27.1 8M1-A – MLF (VDFN) Pin TOP VIEW Pin #1 Notch e (0. BOTTOM VIEW Package Drawing Contact: packagedrawings@atmel.com Atmel AT45DB081D 0. TITLE 8M1-A, 8-pad 1.00mm Body, Thermally Enhanced Plastic Very Thin Dual Flat No Lead Package (VDFN) SIDE VIEW A3 A1 0.08 C COMMON DIMENSIONS ...

Page 49

... SYMBOL Ø Ø TITLE 8S1, 8-lead (0.150” Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) Atmel AT45DB081D Ø Ø END VIEW COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM MAX NOTE 1.35 – 1.75 0.10 – 0.25 0.31 – 0.51 0.17 – ...

Page 50

... EIAJ Drawing EDR-7320 for additional information. 2. Mismatch of the upper and lower dies and resin burrs are not included. 3. Determines the true geometric position. 4. Values b,C apply to plated terminal. The standard thickness of the plating layer shall measure between 0.007 to .021mm. Package Drawing Contact: packagedrawings@atmel.com Atmel AT45DB081D ...

Page 51

... I – April 2008 J – February 2009 K – March 2009 L – April 2009 M – May 2010 3596M–DFLASH–5/10 Atmel AT45DB081D History Initial Release Added Preliminary. Added text, in “Programming the Configuration Register”, to indicate that power cycling is required to switch to “power of 2” page size after the opcode enable has been executed. Added “ ...

Page 52

... Errata 29.1 No Errata Conditions Atmel AT45DB081D 52 3596M–DFLASH–5/10 ...

Page 53

... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...

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