AT45DB041D-SU Atmel, AT45DB041D-SU Datasheet
AT45DB041D-SU
Specifications of AT45DB041D-SU
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AT45DB041D-SU Summary of contents
Page 1
... Green (Pb/Halide-free/RoHS Compliant) Packaging Options 1. Description The AT45DB041D is a 2.5V or 2.7V, serial-interface Flash memory ideally suited for a wide variety of digital voice-, image-, program code- and data-storage applications. The AT45DB041D supports RapidS serial interface for applications requiring very high speed operations. RapidS serial interface is SPI compatible for frequencies MHz ...
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... To allow for simple in-system reprogrammability, the AT45DB041D does not require high input voltages for programming. The device operates from a single power supply, 2.5V to 3.6V or 2.7V to 3.6V, for both the program and read operations. The AT45DB041D is enabled through the chip select pin (CS) and accessed via a three-wire interface consisting of the Serial Input (SI), Serial Output (SO), and the Serial Clock (SCK) ...
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... The metal pad on the bottom of the MLF package is floating. This pad can be a “No Connect” or connected to GND. 3. Block Diagram WP PAGE (256/264 BYTES) BUFFER 1 (256/264 BYTES) SCK CS RESET VCC GND 3595P–DFLASH–09/09 Figure 2- GND 7 VCC FLASH MEMORY ARRAY BUFFER 2 (256/264 BYTES) I/O INTERFACE SI AT45DB041D SOIC Top View SCK 2 7 GND RESET 3 6 VCC ...
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... Memory Array To provide optimal flexibility, the memory array of the AT45DB041D is divided into three levels of granularity comprising of sectors, blocks, and pages. The “Memory Architecture Diagram” illus- trates the breakdown of each level and details the number of pages per sector and block. All program operations to the DataFlash occur on a page-by-page basis ...
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... A0) and a dummy byte. Following the dummy byte, additional clock pulses on the SCK pin will result in data being output on the SO (serial output) pin. 3595P–DFLASH–09/09 specification. The Continuous Array Read bypasses both data buffers and leaves the AT45DB041D . To perform a CAR1 5 ...
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... Following the don’t care bytes, additional pulses on SCK result in data being output on the SO (serial output) pin. The CS pin must remain low during the loading of the opcode, the address bytes, the don’t care bytes, and the reading of data. When the end of a page in main AT45DB041D 6 specification. The Continuous Array Read bypasses both ...
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... The D1H and D3H opcode can be used for lower frequency CAR1 . CAR2 AT45DB041D 7 ...
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... CS pin, the part will erase the selected block of eight pages. The erase operation is internally self-timed and should take place in a maximum time of t this time, the status register will indicate that the part is busy. AT45DB041D 8 . During this time, the status register will indicate that the part is busy. ...
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... PA3/ A14 A13 A12 A11 • • • • • • • • • • • • AT45DB041D PA2/ PA1/ PA0/ A10 A9 A8 Block • • • • • • • • • During this time, the status register • • ...
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... Only those sectors that are not protected or locked down will be erased. The WP pin can be asserted while the device is erasing, but protection will not be activated until the internal erase cycle completes. Command Chip Erase Figure 7-1. Note: AT45DB041D 10 PA6/ PA5/ PA4/ PA3/ A14 A13 ...
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... Sector Protection Register. The status of whether or not sector protection has been enabled or disabled by either the software or the hardware controlled methods can be deter- mined by checking the Status Register. 3595P–DFLASH–09/09 AT45DB041D . During this time ...
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... Disable Sector Protection commands. If the device is power cycled, then the software controlled protection will be disabled. Once the device is powered up, the Enable Sector Protection command should be reissued if sector pro- tection is desired and if the WP pin is not used. AT45DB041D 12 Byte 1 3DH Enable Sector Protection ...
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... When the WP pin is deasserted; however, the sector protection WPE 2 Disable Sector Command Protection Command – Issue Command Issue Command X Not Issued Yet or 2 Issue Command – Issue Command AT45DB041D , then the content of the Sector CC time) as long as the Enable Sec- WPD 3 Sector Protection Status X Disabled Disabled – Enabled X Enabled ...
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... Sector Protection Register.: Table 9-2. Sector Number Protected Unprotected Table 9-3. Sectors 0a, 0b Unprotected Protect Sector 0a Protect Sector 0b (Page 8-255) Protect Sectors 0a (Page 0-7), 0b (Page 8-255) Note: AT45DB041D 14 Sector Protection Register Sector 0 (0a, 0b) 0a (Page 0-7) Bit (1) 1. The default value for bytes 0 through 7 when shipped from Atmel x = don’ ...
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... Command Erase Sector Protection Register Figure 9-2. 3595P–DFLASH–09/09 Byte 1 3DH Erase Sector Protection Register CS Opcode Opcode SI Byte 1 Byte 2 Each transition represents 8 bits AT45DB041D PE Byte 2 Byte 3 Byte 4 2AH 7FH Opcode Opcode Byte 3 Byte 4 , during CFH 15 ...
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... Command Program Sector Protection Register Figure 9-3. Program Sector Protection Register CS Opcode SI Byte 1 Each transition represents 8 bits AT45DB041D 16 , during which time the Status Register will indicate that the device is busy Opcode Opcode Opcode Data Byte Byte 2 Byte 3 Byte 4 Section 9 ...
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... Dummy Byte Read Sector Protection Register Opcode X X Each transition represents 8 bits AT45DB041D Byte 1 Byte 2 Byte 3 32H xxH xxH X Data Byte Data Byte ...
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... Sector Lockdown Register to determine the status of the appropriate sector lockdown bits or bytes and reissue the Sector Lockdown com- mand if necessary. Command Sector Lockdown Figure 10-1. Sector Lockdown CS SI AT45DB041D 18 Byte 1 3DH Opcode Opcode Opcode Byte 1 ...
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... CS SI Opcode SO Each transition represents 8 bits 3595P–DFLASH–09/09 Sector 0 (0a, 0b) (Page 0-7) Bit 7, 6 details the values read from the Sector Lockdown Register. Sector Lockdown Register xx = Dummy Byte Data Byte AT45DB041D 0 (0a, 0b) See Below 0a 0b (Page 8-255) Bit 5, 4 Bit ...
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... Therefore, the contents of the buffer 1 will be altered from its previous state when this command is issued. Figure 10-3. Program Security Register CS Opcode SI Byte 1 Each transition represents 8 bits AT45DB041D 20 Security Register • • • One-time User Programmable , during which time the Status Register will indicate that the device is busy. If the device P ...
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... The CS pin must be low while toggling the SCK pin to load the opcode and 3595P–DFLASH–09/09 Opcode X X Each transition represents 8 bits ), the status register can be read to determine whether the XFR AT45DB041D X Data Byte Data Byte Data Byte ...
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... Main Memory Page to Buffer Transfer, Main Memory Page to Buffer Compare, Buf- fer to Main Memory Page Program, Main Memory Page Program through Buffer, Page Erase, Block Erase, Sector Erase, Chip Erase and Auto Page Rewrite. AT45DB041D 22 ), the status register will indicate that the part is busy. On completion ...
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... The device density is indicated using bits and 2 of the status register. For the AT45DB041D, the four bits are 0111 The decimal value of these four binary bits does not equate to the device density; the four bits represent a combinational code relating to differing densities of DataFlash devices ...
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... RDPD down, the device will return to the normal standby mode. Command Resume from Deep Power-down Figure 12-2. Resume from Deep Power-Down AT45DB041D 24 time. Once the device has entered the Deep Power-down mode, all instructions EDPD CS SI Each transition represents 8 bits time before the device can receive any commands ...
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... Section 13.1). , during which time the Status Register will indicate that the device is P Byte 1 3DH CS Opcode Opcode Opcode SI Byte 1 Byte 2 Byte 3 Each transition represents 8 bits AT45DB041D Section 26. ”Ordering Information” on Byte 2 Byte 3 Byte 4 2AH 80H A6H Opcode Byte 4 25 ...
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... Manufacturer ID codes that are two, three or even four bytes long with the first byte(s) in the sequence being 7FH. A system should detect code 7FH as a “Continuation Code” and continue to read Manufacturer ID bytes. The first non-7FH byte would signify the last byte of Manufacturer ID data. For Atmel (and some other manufacturers), the Manufacturer ID data is comprised of only one byte. AT45DB041D 26 Bit 3 ...
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... Group C can be executed. The Group B commands using buffer 1 should use Group C commands using buffer 2 and vice versa. Finally, during the internally self- timed portion of a Group D command, only the Status Register Read command should be executed. 3595P–DFLASH–09/09 AT45DB041D 27 ...
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... Buffer 1 to Main Memory Page Program without Built-in Erase Buffer 2 to Main Memory Page Program without Built-in Erase Page Erase Block Erase Sector Erase Chip Erase Main Memory Page Program Through Buffer 1 Main Memory Page Program Through Buffer 2 AT45DB041D 28 Read Commands Program and Erase Commands Opcode D2H E8H 03H ...
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... Note: 3595P–DFLASH–09/09 Protection and Security Commands Additional Commands (1) Legacy Commands 1. These legacy commands are not recommended for new designs. AT45DB041D Opcode 3DH + 2AH + 7FH + A9H 3DH + 2AH + 7FH + 9AH 3DH + 2AH + 7FH + CFH 3DH + 2AH + 7FH + FCH 32H 3DH + 2AH + 7FH + 30H ...
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... B9h ABh D1h D2h D3h D4h D6h D7h E8h Notes Don’t Care AT45DB041D 30 Address Byte Address Byte N/A N/A N/A N/A N/A N ...
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... N/A N/A N/A N/A N/A N N/A N Don’t Care AT45DB041D Address Byte N/A N Additional Don’t Care Bytes B N N/A x N/A x N/A x N/A x N/A x N/A x N/A x N/A x N/A x N/A B N/A x N/A B N/A B N/A x N/A B N/A x N/A x N/A N/A N/A ...
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... The regulator needs to supply this peak current requirement. An under specified regulator can cause current starvation. Besides increasing system noise, current starvation during program- ming or erase can lead to improper operation and possible data corruption. AT45DB041D 32 . During power-up, the internal Power-on Reset circuitry keeps the device in ...
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... Operating Temperature (Case) V Power Supply CC 3595P–DFLASH–09/09 *NOTICE: + 0.6V CC AT45DB041D (2.5V Version) Ind. -40° 85° C 2.5V to 3.6V AT45DB041D Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam- age to the device. The "Absolute Maximum Rat- ings" are stress ratings only and functional ...
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... IH V Output Low Voltage OL V Output High Voltage OH Notes during a buffer read maximum @ 20 MHz. CC1 2. All inputs (SI, SCK, CS#, WP#, and RESET#) are guaranteed by design to be 5-Volt tolerant. AT45DB041D 34 Condition Min CS, RESET all IH inputs at CMOS levels CS, RESET all IH inputs at CMOS levels MHz ...
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... RESET Recovery Time REC 3595P–DFLASH–09/09 AT45DB041D (2.5V Version) AT45DB041D Min Typ Max Min 6.8 6.8 6.8 6.8 0.1 0.1 0.1 0 200 200 1 AT45DB041D Typ Max Units 66 MHz 66 MHz 33 MHz ns ns V/ns V/ µs 1 µs 3 µs 35 µs 200 µs 200 µ 1 µs 1 µ ...
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... SPI Mode 0 and SPI Mode 3, respectively. Waveform 3 and waveform 4 illustrate general timing diagram for RapidS serial interface. These are similar to waveform 1 and waveform 2, except that output SO is not restricted to become valid during the t imum frequency = 66 MHz) of the RapidS serial case. AT45DB041D 36 2.4V AC DRIVING 1 ...
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... SO SI 3595P–DFLASH–09/ CSS VALID OUT VALID CSS VALID OUT VALID MHz) MAX CSS VALID OUT VALID MHz) MAX CSS VALID OUT VALID IN AT45DB041D CSH t DIS HIGH IMPEDANCE CSH t DIS HIGH IMPEDANCE CSH t DIS HIGH IMPEDANCE CSH t DIS HIGH IMPEDANCE 37 ...
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... Master clocks out second bit of BYTE-MOSI on the same rising edge of SCK. D. Last bit of BYTE-MOSI is clocked out from the Master. E. Last bit of BYTE-MOSI is clocked into the slave. F. Slave clocks out first bit of BYTE-SO. G. Master clocks in first bit of BYTE-SO. H. Slave clocks out second bit of BYTE-SO. I. Master clocks in last bit of BYTE-SO. AT45DB041D ...
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... HIGH IMPEDANCE CMD 8 bits 8 bits Page Address Bits (A18 - A8) CMD 8 bits 8 bits 8 bits Don’t Care Page Address Bits (PA10 - PA0) AT45DB041D t REC t RST HIGH IMPEDANCE 8 bits LSB Byte/Buffer Address (A7 - A0/BFA7 - BFA0 Byte/Buffer Address (BA8 - BA0/BFA8 - BFA0) t CSS LSB 39 ...
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... Buffer Write CS SI (INPUT) CMD 22.2 Buffer to Main Memory Page Program (Data from Buffer Programmed into Flash Page (INPUT) Each transition represents 8 bits AT45DB041D 40 FLASH MEMORY ARRAY BUFFER TO MAIN MEMORY PAGE PROGRAM BUFFER (256/264 BYTES) BUFFER WRITE I/O INTERFACE SI BINARY PAGE SIZE ...
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... I/O INTERFACE SO ADDRESS FOR BINARY PAGE SIZE A15-A8 A18-A16 A7-A0 PA10-7 PA6-0, BA8 BA7-0 BINARY PAGE SIZE A18- DON'T CARE BITS CMD PA10-7 AT45DB041D MAIN MEMORY PAGE TO BUFFER 2 BUFFER 2 (256/264 BYTES) BUFFER 2 READ Dummy Bytes n n+1 Starts reading page data into buffer ...
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... Continuous Array Read (Legacy Opcode E8H SCK OPCODE MSB HIGH-IMPEDANCE SO 24.2 Continuous Array Read (Opcode 0BH SCK OPCODE MSB HIGH-IMPEDANCE SO AT45DB041D 42 BINARY PAGE SIZE 16 DON'T CARE + BFA7-BFA0 CMD X X..X, BFA8 BFA7 ADDRESS BITS 32 DON'T CARE BITS MSB MSB ADDRESS BITS A18 - A0 ...
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... OPCODE ADDRESS BITS A18- MSB ADDRESS BITS 32 DON'T CARE BITS MSB MSB ADDRESS BITS BINARY PAGE SIZE = 16 DON'T CARE + BFA7-BFA0 STANDARD DATAFLASH PAGE SIZE = 15 DON'T CARE + BFA8-BFA0 MSB MSB AT45DB041D DATA BYTE MSB MSB DATA BYTE MSB DON'T CARE DATA BYTE 1 ...
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... SCK MSB HIGH-IMPEDANCE SO 24.7 Read Sector Protection Register (Opcode 32H SCK MSB HIGH-IMPEDANCE SO 24.8 Read Sector Lockdown Register (Opcode 35H SCK MSB HIGH-IMPEDANCE SO AT45DB041D ADDRESS BITS BINARY PAGE SIZE = 16 DON'T CARE + BFA7-BFA0 STANDARD DATAFLASH PAGE SIZE = OPCODE 15 DON'T CARE + BFA8-BFA0 MSB ...
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... HIGH-IMPEDANCE SO Note: Each transition 3595P–DFLASH–09/ OPCODE DON'T CARE MSB OPCODE STATUS REGISTER DATA MSB OPCODE 9FH 1FH DEVICE ID BYTE 1 shown for SI and SO represents one byte (8 bits) AT45DB041D DATA BYTE MSB MSB STATUS REGISTER DATA MSB MSB DEVICE ID BYTE 2 00H 45 ...
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... A page can be written using either a Main Memory Page Program operation or a Buffer Write operation followed by a Buffer to Main Memory Page Program operation. 3. The algorithm above shows the programming of a single page. The algorithm will be repeated sequentially for each page within the entire array. AT45DB041D 46 START provide address ...
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... MAIN MEMORY PAGE TO BUFFER TRANSFER (53H, 55H) BUFFER WRITE (84H, 87H) BUFFER TO MAIN MEMORY PAGE PROGRAM (83H, 86H) (2) AUTO PAGE REWRITE (58H, 59H) INCREMENT PAGE (2) ADDRESS POINTER END AT45DB041D If planning to modify multiple bytes currently stored within a page of the Flash array 47 ...
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... AT45DB041D-SU-SL954 (4) AT45DB041D-SU-SL955 AT45DB041D-MU-2.5 AT45DB041D-SSU-2.5 AT45DB041D-SU-2.5 Notes: 1. The shipping carrier option is not marked on the devices. 2. Standard parts are shipped with the page size set to 264 bytes. The user is able to configure these parts to a 256-byte page size if desired. 3. Parts ordered with suffix SL954 are shipped in bulk with the page size set to 256 bytes. Parts will have a 954 or SL954 marked on them ...
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... Body, Very Thin Dual Flat Package No Lead MLF 8S1 8-lead, 0.150” Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC) 8S2 8-lead, 0.209” Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC) 3595P–DFLASH–09/09 Package Type ™ (VDFN) AT45DB041D 49 ...
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... Packaging Information 27.1 8M1-A – MLF (VDFN) Pin TOP VIEW Pin #1 Notch e (0. BOTTOM VIEW Package Drawing Contact: packagedrawings@atmel.com AT45DB041D 0. TITLE 8M1-A, 8-pad 1.00 mm Body, Thermally Enhanced Plastic Very Thin Dual Flat No Lead Package (VDFN) SIDE VIEW A3 A1 0.08 C COMMON DIMENSIONS ...
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... These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 R 3595P–DFLASH–09/ TITLE 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) AT45DB041D Ø Ø END VIEW COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM MAX SYMBOL A1 0.10 – 0.25 DRAWING NO ...
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... Notes: 1. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information. 2. Mismatch of the upper and lower dies and resin burrs aren't included. 3. Determines the true geometric position. 4. Values b,C apply to plated terminal. The standard thickness of the plating layer shall measure between 0.007 to .021 mm. Package Drawing Contact: packagedrawings@atmel.com AT45DB041D TOP VIEW ...
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... Max and 35 ns, respectively. DIS Changed Deep Power-Down Current values - Increased typical value from 5 µ µA. - Increased maximum value from 15 µ µA. Updated Absolute Maximum Ratings Removed Chip Erase Errata Pg50: replace package drawing as per the attached AT45DB041D Table 15-6. Table 15-7. Table Table 53 ...
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... Errata 29.1 No Errata Conditions AT45DB041D 54 3595P–DFLASH–09/09 ...
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... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...