IC FLASH 32MBIT 110NS 64FBGA

 

MT28F320J3FS-11 ET TR

Manufacturer Part NumberMT28F320J3FS-11 ET TR
DescriptionIC FLASH 32MBIT 110NS 64FBGA
ManufacturerMicron Technology Inc
MT28F320J3FS-11 ET TR datasheets

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Specifications of MT28F320J3FS-11 ET TR

Format - MemoryFLASHMemory TypeFLASH
Memory Size32M (4Mx8, 2Mx16)Speed110ns
InterfaceParallelVoltage - Supply2.7 V ~ 3.6 V
Operating Temperature-40°C ~ 85°CPackage / Case64-FBGA
Lead Free Status / RoHS StatusContains lead / RoHS non-compliantOther names557-1002-2
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Table 1:
Pin/Ball Descriptions
56-PIN TSOP
64-BALL FBGA
NUMBERS
NUMBERS
55
G8
14, 2, 29
B4, B8, H1
16
D4
54
F8
32, 28, 27, 26,
G2, A1, B1, C1,
25, 24, 23, 22,
D1, D2, A2, C2,
20, 19, 18, 17,
A3, B3, C3, D3,
13, 12, 11, 10, 8,
C4, A5, B5, C5,
7, 6, 5, 4, 3, 1,
D7, D8, A7, B7,
30
C7, C8, A8, G1
31
F1
15
A4
33, 35, 38, 40,
F2, E2, G3, E4,
44, 46, 49, 51,
E5, G5, G6, H7,
34, 36, 39, 41,
E1, E3, F3, F4,
45, 47, 50, 52
F5, H5, G7, E7
53
E8
43
G4
9, 37
H3, A6
21, 42, 48
B2, H4, H6
1, 30, 56
A1, G1, H8
—
B6, C6, D5, D6,
E6, F6, F7, H2
09005aef80b5a323
MT28F640J3.fm – Rev. N 3/05 EN
SYMBOL
TYPE
WE#
Input
Write Enable: Determines if a given cycle is a WRITE cycle. If WE# is
LOW, the cycle is either a WRITE to the command execution logic
(CEL) or to the memory array. Addresses and data are latched on
the rising edge of the WE# pulse.
CE0, CE1,
Input
Chip Enable: Three CE pins enable the use of multiple Flash devices
CE2
in the system without requiring additional logic. The device can be
configured to use a single CE signal by tying CE1 and CE2 to
ground and then using CE0 as CE. Device selection occurs with the
first edge of CE0, CE1, or CE2 (CEx) that enables the device. Device
deselection occurs with the first edge of CEx that disables the
device (see Table 2 on page 11).
RP#
Input
Reset/Power-Down: When LOW, RP# clears the status register, sets
the ISM to the array read mode, and places the device in deep
power-down mode. All inputs, including CEx, are “Don’t Care,”
and all outputs are High-Z. RP# must be held at V
other modes of operation.
OE#
Input
Output Enables: Enables data ouput buffers when LOW. When
OE# is HIGH, the output buffers are disabled.
A0−A21/
Input
Address inputs during READ and WRITE operations.
(A22)
A0 is only used in x8 mode and will be a NC in x16 mode (the input
(A23)
buffer is turned off when BYTE = HIGH).
A22 (pin 1, ball A8) is only available on the 64Mb and 128Mb
devices.
A23 (pin 30, ball G1) is only available on the 128Mb device.
BYTE#
Input
BYTE# low places the device in the x8 mode. BYTE# high places the
device in the x16 mode and turns off the A0 input buffer. Address
A1 becomes the lowest order address in x16 mode.
V
Input
Necessary voltage for erasing blocks, programming data, or
PEN
configuring lock bits. Typically, V
≤ V
V
, this pin enables hardware write protect.
PEN
PENLK
DQ0–
Input/
Data I/O: Data output pins during any READ operation or data
DQ15
Output
input pins during a WRITE. DQ8–DQ15 are not used in byte mode
(BYTE = LOW).
STS
Output Status: Indicates the status of the ISM. When configured in level
mode (default), STS acts as a RY/BY# pin. When configured in its
pulse mode, it can pulse to indicate program and/or erase
completion. Tie STS to V
V
Q
Supply V
Q controls the output voltages. To obtain output voltage
CC
CC
compatible with system data bus voltages, connect V
system supply voltage.
V
Supply Power Supply: 2.7V to 3.6V.
CC
V
Supply Ground.
SS
NC
—
No Connect: These may be driven or left unconnected. Pin 1 and
ball A8 are NCs on the 32Mb device. Pin 30 and ball G1 are NCs on
the 32Mb and 64Mb devices.
DNU
—
Do Not Use: Must float to minimize noise.
10
128Mb, 64Mb, 32Mb
Q-FLASH MEMORY
DESCRIPTION
is connected to V
PEN
Q through a pull-up resistor.
CC
Micron Technology, Inc., reserves the right to change products or specifications without notice.
during all
IH
. When
CC
Q to the
CC
©2000 Micron Technology. Inc.

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