MT29F2G08AABWP-ET Micron Technology Inc, MT29F2G08AABWP-ET Datasheet
MT29F2G08AABWP-ET
Specifications of MT29F2G08AABWP-ET
Related parts for MT29F2G08AABWP-ET
MT29F2G08AABWP-ET Summary of contents
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... NAND Flash Memory MT29F2G08AABWP/MT29F2G16AABWP MT29F4G08BABWP/MT29F4G16BABWP MT29F8G08FABWP Features • Organization: • Page size: x8: 2,112 bytes (2,048 + 64 bytes) x16: 1,056 words (1,024 + 32 words) • Block size: 64 pages (128K + 4K bytes) • Device size: 2Gb: 2,048 blocks; 4Gb: 4,096 blocks; 8Gb: 8,192 blocks • Read performance: • ...
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... Micron Parametric Part Search Web site at http://www.micron.com/partsearch If the device required is not on this list, contact the factory. PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29b__1.fm - Rev 8Gb: x8/x16 Multiplexed NAND Flash Memory ® NAND Flash devices are available in several different configurations and A A ...
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... Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 V Power Cycling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 CC Timing Diagrams .42 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29bTOC.fm - Rev 8Gb: x8/x16 Multiplexed NAND Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. 3 Table of Contents ©2004 Micron Technology, Inc. All rights reserved. ...
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... Figure 50: INTERNAL DATA MOVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Figure 51: PROGRAM PAGE CACHE MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29bLOF.fm - Rev 8Gb: x8/x16 Multiplexed NAND Flash Memory only .21 CC Micron Technology, Inc., reserves the right to change products or specifications without notice. 4 List of Figures ©2004 Micron Technology, Inc. All rights reserved. ...
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... BLOCK ERASE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Figure 54: RESET Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Figure 55: 48-Pin TSOP Type .56 PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29bLOF.fm - Rev 8Gb: x8/x16 Multiplexed NAND Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. 5 List of Figures ©2004 Micron Technology, Inc. All rights reserved. ...
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... Table 18: AC Characteristics: Normal Operation .41 Table 19: PROGRAM/ERASE Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29bLOT.fm - Rev 8Gb: x8/x16 Multiplexed NAND Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. 6 List of Tables ©2004 Micron Technology, Inc. All rights reserved. ...
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... NAND technology provides a cost-effective solution for applications requiring high- density solid-state storage. The MT29F2G08AxB and MT29F2G16AxB are 2Gb NAND Flash memory devices. The MT29F4G08BxB and MT29F4G16BxB are two-die stacks that operate as a single 4Gb device. The MT29F8G08FAB is a four-die stack that operates as two independent 4Gb devices (MT29F4G08BxB), providing a total storage capacity of 8Gb in a single, space-saving package ...
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... NC 24 Notes: 1. CE2# and R/B2# on 8Gb device only. These pins are NC for other configurations. 2. The PRE function is not supported on extended-temperature devices. PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29b__2.fm - Rev 8Gb: x8/x16 Multiplexed NAND Flash Memory Address Register I/O Status Register Command Register 8 ...
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... ERASE operation. The pin is also used during a READ operation to indicate when data is being transferred from the array into the serial data register. Once these operations have completed, the R/B# returns to the High-Z state. In the 8Gb configuration, R/B# is for the 4Gb of memory enabled by CE#; R/B2# is for the 4Gb of memory enabled by CE2 The V pin is the power supply pin ...
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... This provides a memory device with a low pin count. The internal memory array is accessed on a page basis. When doing reads, a page of data is copied from the memory array into the data register. Once copied to the data register, data is output sequentially, byte-by-byte on x8 devices, or word-by-word on x16 devices ...
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... A27 (4Gb: A28) 0 Block Address Note: Block address and page address = actual page address. PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29b__2.fm - Rev 8Gb: x8/x16 Multiplexed NAND Flash Memory A1 7 A18 page 63-0 Block Address Page Address within a block page 63-0 ...
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... RA27 RA26 Fourth Fifth LOW LOW Note: CAx = column address; RAx = row address. PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29b__2.fm - Rev 8Gb: x8/x16 Multiplexed NAND Flash Memory 2,112 bytes 2,048 64 2,048 64 64 pages = 1 block 1 Block 1 page 1 block 1 device = (2K + 64) bytes x 64 pages ...
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... LOW LOW Notes: 1. CAx = column address; RAx = row address. 2. I/O[15:8] are not used during the addressing sequence and should be driven LOW. PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29b__2.fm - Rev 8Gb: x8/x16 Multiplexed NAND Flash Memory 1,056 words 1,024 32 1,024 32 64 pages = 1 block ...
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... RA18 Fourth RA27 RA26 LOW LOW Fifth Notes: 1. Die address boundary – 2Gb 2Gb – 4Gb. PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29b__2.fm - Rev 8Gb: x8/x16 Multiplexed NAND Flash Memory 2,112 bytes 2,048 64 2,048 64 64 pages = 1 block 1 Block 1 page 1 block 1 device = (2K + 64) bytes x 64 pages ...
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... LOW LOW Notes: 1. Die address boundary – 2Gb 2Gb – 4Gb. 2. I/O[15:8] are not used during the addressing sequence and should be driven LOW. PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29b__2.fm - Rev 8Gb: x8/x16 Multiplexed NAND Flash Memory 1,056 words 1,024 32 1,024 32 1 Block ...
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... Care” operations. The CE# “Don’t Care” operation allows the NAND Flash to reside on the same asynchro- nous memory bus as other Flash or SRAM devices. Other devices on the memory bus can then be accessed while the NAND Flash is busy with internal operations. This capa- bility is important for designs that require multiple NAND Flash devices on the same bus ...
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... Data is input on I/O[7:0] for x8 devices, and I/O[15:0] on x16 devices. See Figure 36 on page 43 for additional data input details. READs After a READ command is sent to the memory device, data is transferred from the mem- ory array to the data register in register clocked out of the part by RE# going LOW. See Figure 39 on page 44 for detailed timing information ...
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... R dependent on external capacitance and resistive loading and output transistor impedance primarily dependent on external pull-up resistor and external capacitive loading ≈ 10ns at 3.3V See TC values in Figure 15 on page 19 for approximate Rp value and TC. PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29b__2.fm - Rev 8Gb: x8/x16 Multiplexed NAND Flash Memory V (MAX) – V (MAX Σ ...
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... I 1.50mA 1.00mA 0.50mA 0.00mA Figure 15: TC vs. Rp 1.20µs 1.00µs 800ns T 600ns 400ns 200ns 0ns PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29b__2.fm - Rev 8Gb: x8/x16 Multiplexed NAND Flash Memory 0 2000 4000 6000 8000 10000 2kΩ 4kΩ 6kΩ 8kΩ 10kΩ ...
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... Notes: 1. WP# should be biased to CMOS HIGH or LOW for standby. 2. PRE should be tied to V The PRE function is not supported on extended-temperature devices. 3. Mode selection settings for this table Logic level HIGH Logic level LOW PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29b__2.fm - Rev 8Gb: x8/x16 Multiplexed NAND Flash Memory 1 RE# WP# PRE H X ...
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... Power-On AUTO-READ During power-on, with the PRE pin at V first page of the memory array to the data register without requiring a command or address-input sequence tor initiates the power-on AUTO-READ function. R/B# will stay LOW ( See Table 18 on page 41 for the HIGH, RE# can be pulsed to output the first page of data. ...
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... PROGRAM FOR INTERNAL DATA MOVE. See Tables 4 and 5 for definition of die address boundaries. 3. RANDOM DATA READ command limited to use within a single page. 4. RANDOM DATA INPUT for PROGRAM command limited to use within a single page. PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29b__2.fm - Rev 8Gb: x8/x16 Multiplexed NAND Flash Memory Cycle 1 00h 31h 1 3Fh ...
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... CE# WE# ALE R/B# RE# I/Ox 00h Address (5 Cycles) PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29b__2.fm - Rev 8Gb: x8/x16 Multiplexed NAND Flash Memory t R 30h Micron Technology, Inc., reserves the right to change products or specifications without notice. 23 Command Definitions t R (transfer from Flash array rate. (See Figure 18 Data Output (Serial Access) Don‘ ...
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... R/B# will stay LOW up to depending on whether the previous memory-to-data-register transfer was completed prior to issuing the next 31h command. If the data transfer from memory to the data reg- ister is not completed before the 31h command is issued, R/B# stays LOW until the transfer is complete ...
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Figure 20: PAGE READ CACHE MODE CLE CE# WE# ALE t R R/B# RE# I/Ox 00h Address (5 Cycles) 30h t DCBSYR1 t DCBSYR2 31h Data Output (Serial Access) 31h Data Output (Serial Access) t DCBSYR2 3fh Data Output (Serial ...
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... READ ID Operation CLE CE# WE# ALE RE# I/Ox Notes: 1. See Table 8 on page 27. PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29b__2.fm - Rev 8Gb: x8/x16 Multiplexed NAND Flash Memory WHR t REA 90h 00h Address, 1 Cycle Manufacturer Micron Technology, Inc., reserves the right to change products or specifications without notice. 26 ...
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... READ STATUS (70h) command is repeatedly issued after each RE# toggle. Additional details regarding READ STATUS implementation are available in Micron technical note TN-29-13 at: www.micron.com/products/nand/massstorage/technote. PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29b__2.fm - Rev 8Gb: x8/x16 Multiplexed NAND Flash Memory I/O7 I/O6 I/O5 I/O4 I/O3 ...
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... Status register bit 6 is “1” when the cache is ready to accept new data. R/B# follows bit 6. See Figure 20 on page 25, and Figure 25 on page 30. PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29b__2.fm - Rev 8Gb: x8/x16 Multiplexed NAND Flash Memory t CLEA t CLR t REA Status ...
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... PROGRAM and READ STATUS Operation R/B# 80h Address (5 cycles) I/Ox Figure 24: RANDOM DATA INPUT R/B# I/Ox D 80h Address (5 cycles) PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29b__2.fm - Rev 8Gb: x8/x16 Multiplexed NAND Flash Memory t PROG D 10h IN D 85h Address (2 cycles Command Definitions t PROG. The READ STATUS ...
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... Notes: 1. See Note 3, Table 19 on page 41. 2. Check I/O[6:5] for internal Ready/Busy. Check I/O[1:0] for pass fail. RE# can stay LOW or pulse multiple times after a 70h command. PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29b__2.fm - Rev 8Gb: x8/x16 Multiplexed NAND Flash Memory t CBSY Address/ Address/ ...
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... The written column addresses are ignored even though all five ADDRESS cycles are required. The memory device is now ready to accept the INTERNAL DATA MOVE (85h-10h) com- mand. Please refer to the description of this command in the following section. INTERNAL DATA MOVE 85h-10h After the READ for INTERNAL DATA MOVE command has been issued and R/B# goes HIGH, the INTERNAL DATA MOVE command can be written to the command register ...
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... Figure 27: INTERNAL DATA MOVE with RANDOM DATA INPUT R/B# Address I/Ox 00h 35h (5 cycles) PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29b__2.fm - Rev 8Gb: x8/x16 Multiplexed NAND Flash Memory t R Address 85h (5 cycles Address 85h Data 85h (5 cycles) Unlimited number ...
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... BLOCK ERASE Operation CLE CE# WE# ALE R/B# RE# I/Ox 60h Address Input (3 Cycles) PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29b__2.fm - Rev 8Gb: x8/x16 Multiplexed NAND Flash Memory t BERS erase time. t BERS D0h 33 Command Definitions 70h Status I ERASE successful I ERASE error Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... RESET Operation RESET FFh The RESET command is used to put the memory device into a known condition and to abort a command sequence in progress. RANDOM READ, PROGRAM, and ERASE commands can be aborted while the device is in the busy state. The contents of the memory location being programmed or the block being erased are no longer valid ...
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... WE# I/Ox WP# R/B# Figure 32: PROGRAM Enable WE# I/Ox WP# R/B# PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29b__2.fm - Rev 8Gb: x8/x16 Multiplexed NAND Flash Memory t WW 60h D0h t WW 60h D0h t WW 80h 10h Micron Technology, Inc., reserves the right to change products or specifications without notice. 35 Command Definitions ...
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... Figure 33: PROGRAM Disable WE# I/Ox WP# R/B# PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29b__2.fm - Rev 8Gb: x8/x16 Multiplexed NAND Flash Memory t WW 80h 10h Micron Technology, Inc., reserves the right to change products or specifications without notice. 36 Command Definitions ©2004 Micron Technology, Inc. All rights reserved. ...
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... Over time, some memory locations may fail to program or erase properly. In order to ensure that data is stored properly over the life of the Flash device, certain precautions must be taken, such as: • ...
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... WP# provides additional hardware protection. WP# should be kept at V allowed for the Flash to initialize before executing any commands. (See Figure 17 on page 21.) PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29b__2.fm - Rev 8Gb: x8/x16 Multiplexed NAND Flash Memory Symbol V Supply voltage on any pin relative to Vss IN V ...
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... Table 15: Capacitance Description Input capacitance Input/output capacitance (I/O) Notes: 1. These parameters are verified in device characterization and are not 100 percent tested. 2. Test conditions: T PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29b__2.fm - Rev 8Gb: x8/x16 Multiplexed NAND Flash Memory Conditions Symbol t CYCLE = 30ns, Icc1 CE ...
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... WE# for data input. 2. For PROGRAM PAGE CACHE MODE operations, the x16 AC characteristics apply for both x16 and x8 devices. PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29b__2.fm - Rev 8Gb: x8/x16 Multiplexed NAND Flash Memory = 3.0V ±10 3.3V ±10%) CC ...
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... Notes: 1. Eight total to the same page CBSY MAX time depends on timing between internal program completion and data in LPROG = time (last page) – data load time (last page). PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29b__2.fm - Rev 8Gb: x8/x16 Multiplexed NAND Flash Memory x16 Symbol Min Max CEA – ...
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... I/Ox Note: x16: I/O[15:8] must be set to “0. Figure 35: ADDRESS LATCH Cycle CLE CE# WE# ALE I/Ox Note: x16: I/O [15:8] must be set to “0.” PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29b__2.fm - Rev 8Gb: x8/x16 Multiplexed NAND Flash Memory t t CLS CLH ALH ALS ...
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... Figure 36: INPUT DATA LATCH CLE CE# ALE WE# I/Ox Notes Figure 37: SERIAL ACCESS Cycle After READ t CEA CE# t REA t RP RE# I/ R/B# PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29b__2.fm - Rev 8Gb: x8/x16 Multiplexed NAND Flash Memory t ALS Final = 2,111 (x8) or 1,055 (x16). t REA t REH ...
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... Figure 38: STATUS READ Cycle CLE CE# WE# RE# I/Ox Figure 39: PAGE READ CLE CE WE# ALE RE# Col I/Ox 00h Add 1 Add 2 R/B# PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29b__2.fm - Rev 8Gb: x8/x16 Multiplexed NAND Flash Memory t CLEA t CLR t t CLH CLS WHR 70h t WB Col ...
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... Address (5 Cycles) Figure 41: RANDOM DATA READ CLE CE# WE# ALE RE# Col Col Row I/Ox 00h Add 1 Add 2 Add 1 R/B# PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29b__2.fm - Rev 8Gb: x8/x16 Multiplexed NAND Flash Memory t CEA t REA t R 30h Row Row D OUT 30h Add 2 Add 3 ...
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Figure 42: PAGE READ CACHE MODE Timing Diagram, Part CLE t t CLS CLH CE WE# ALE RE Col Col Row Row 00h I/Ox Add 1 Add ...
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Figure 43: PAGE READ CACHE MODE Timing Diagram, Part CLE t t CLS CLH CE# WE# t CEA ALE REA D ...
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Figure 44: PAGE READ CACHE MODE Timing without R/B#, Part CLE t CLS t CLH CE WE# ALE RE Col Col Row Row Row I/Ox 00h Add ...
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Figure 45: PAGE READ CACHE MODE Timing without R/B#, Part ...
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... ALE RE# I/Ox 90h Address, 1 Cycle Figure 47: Program Operation with CE# “Don’t Care” CLE CE# WE# ALE I/Ox 80h Address (5 Cycles) PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29b__2.fm - Rev 8Gb: x8/x16 Multiplexed NAND Flash Memory WHR REA 00h Byte 0 Byte 1 1 Manufacturer ID Device ...
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... CLE CE WE# ALE RE# Col Col I/Ox 80h Add 1 Add 2 SERIAL DATA INPUT Command R/B# PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29b__2.fm - Rev 8Gb: x8/x16 Multiplexed NAND Flash Memory t ADL Row Row Row Add 1 Add 2 Add Byte Serial Input x8 device 2,111 byte x16 device 1,055 byte Micron Technology, Inc ...
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... WE# ALE RE# Col Col Row Row I/Ox 00h Add 1 Add 2 Add 1 Add 2 R/B# PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29b__2.fm - Rev 8Gb: x8/x16 Multiplexed NAND Flash Memory t ADL Row D D Col IN IN 85h Add 3 N N+1 Add 1 RANDOM DATA Column Address Serial Input ...
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... Add 1 Add 2 Add 3 Add 1 Add 2 SERIAL DATA INPUT R/B# Last Page - 1 Note: PROGRAM PAGE CACHE MODE operations must not cross die address boundaries. PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29b__2.fm - Rev 8Gb: x8/x16 Multiplexed NAND Flash Memory CBSY Col 80h 15h Add ...
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Figure 52: PROGRAM PAGE CACHE MODE Ending on 15h CLE CE WE# ALE RE# Col Col Row Row Row D IN I/Ox 80h Add 1 Add 2 Add 1 Add 2 Add 3 N SERIAL DATA Serial Input ...
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... AUTO BLOCK ERASE SETUP Command Notes: 1. See Table 8 on page 27 for actual values. Figure 54: RESET Operation CLE CE# WE# R/B# I/Ox PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29b__2.fm - Rev 8Gb: x8/x16 Multiplexed NAND Flash Memory BERS Row D0h Add 3 ERASE Command Busy RST ...
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... This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range for production devices. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29b__2.fm - Rev 8Gb: x8/x16 Multiplexed NAND Flash Memory 20.00 ±0.25 18.40 ±0.08 SEE DETAIL A 1.20 MAX ® ...
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... Updated package drawing. Rev 4/05 • Initial Release PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29b__2.fm - Rev 8Gb: x8/x16 Multiplexed NAND Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. 57 Revision History ©2004 Micron Technology, Inc. All rights reserved. ...