IC FLASH 4MBIT 80NS 40TSOP

MT28F004B3VG-8 BET TR

Manufacturer Part NumberMT28F004B3VG-8 BET TR
DescriptionIC FLASH 4MBIT 80NS 40TSOP
ManufacturerMicron Technology Inc
MT28F004B3VG-8 BET TR datasheet
 


Specifications of MT28F004B3VG-8 BET TR

Format - MemoryFLASHMemory TypeFLASH - Nor
Memory Size4M (512K x 8)Speed80ns
InterfaceParallelVoltage - Supply3 V ~ 3.6 V
Operating Temperature-40°C ~ 85°CPackage / Case40-TSOP
Lead Free Status / RoHS StatusContains lead / RoHS non-compliant  
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FLASH MEMORY
Features
• Seven erase blocks:
16KB/8K-word boot block (protected)
Two 8KB/4K-word parameter blocks
Four main memory blocks
• Smart 3 technology (B3):
3.3V ±0.3V V
CC
V
3.3V ±0.3V
application programming
PP
V
5V ±10%
application/production programming
PP
• Compatible with 0.3µm Smart 3 device
• Advanced 0.18µm CMOS floating-gate process
• Address access time: 80ns
• 100,000 ERASE cycles
• Industry-standard pinouts
• Inputs and outputs are fully TTL-compatible
• Automated write and erase algorithm
• Two-cycle WRITE/ERASE sequence
• Byte- or word-wide READ and WRITE
(MT28F400B3, 256K x 16/512K x 8)
• Byte-wide READ and WRITE only
(MT28F004B3, 512K x 8)
TSOP and SOP packaging options
Options
• Timing
• 80ns access
• Configurations
• 1 Meg x 8
• 512K x 16/1 Meg x 8
• Boot Block Starting Word Address
• Top (3FFFFh)
• Bottom (00000h)
• Operating Temperature Range
• Extended (-40ºC to +85ºC)
• Packages
MT28F004B3
Plastic 40-pin (standard) TSOP Type I
Plastic 40-pin (lead free) TSOP Type
MT28F400B3
Plastic 48-pin (standard) TSOP Type I
Plastic 48-pin (lead free) TSOP Type I
Plastic 44-pin (standard) SOP
Plastic 44-pin (lead free) SOP
NOTE:
1. This generation of devices does not support 12V
V
production programming; however, 5V
PP
application production programming can be
used with no loss of performance.
2. Contact Factory for availability
09005aef8114a789
F45.fm - Rev. E 6/04 EN
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
SMART 3 BOOT BLOCK FLASH MEMORY
MT28F004B3
MT28F400B3
3V ONLY, DUAL SUPPLY (SMART 3)
40-Pin TSOP Type I
1
GENERAL DESCRIPTION
The MT28F004B3 (x8) and MT28F400B3 (x16/x8)
are nonvolatile, electrically block-erasable (flash),
Marking
programmable memory devices containing 4,194,304
bits organized as 262,144 words (16 bits) or 524,288
-8
bytes (8 bits). Writing or erasing the device is done with
either a 3.3V or 5V V
MT28F004B3
performed with a 3.3V V
MT28F400B3
advances, 5V V
duction programming. These devices are fabricated
T
with Micron’s advanced 0.18µm CMOS floating-gate
B
process.
The MT28F004B3 and MT28F400B3 are organized
ET
into seven separately erasable blocks. To ensure that
critical firmware is protected from accidental erasure
VG
or overwrite, the devices feature a hardware-protected
I
VP
boot block. Writing or erasing the boot block requires
either applying a super-voltage to the RP# pin or driv-
WG
ing WP# HIGH in addition to executing the normal
WP
write or erase sequences. This block may be used to
2
SG
store code implemented in low-level system recovery.
2
SP
The remaining blocks vary in density and are written
and erased with no additional security measures.
V
PP
Refer to Micron’s Web site (www.micron.com/flash)
for the latest data sheet.
1
4Mb
48-Pin TSOP Type I
44-Pin SOP
voltage, while all operations are
PP
. Due to process technology
CC
is optimal for application and pro-
PP
Part Number Example:
MT28F400B3SG-8 T
©2003 Micron Technology, Inc. All rights reserved.

MT28F004B3VG-8 BET TR Summary of contents

  • Page 1

    ... Contact Factory for availability 09005aef8114a789 F45.fm - Rev. E 6/04 EN PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. SMART 3 BOOT BLOCK FLASH MEMORY MT28F004B3 MT28F400B3 3V ONLY, DUAL SUPPLY (SMART 3) 40-Pin TSOP Type I 1 ...

  • Page 2

    ... A0 40-Pin TSOP Type I A16 1 A15 2 A14 3 A13 4 A12 5 A11 WE# 9 RP# 10 VPP 11 WP# 12 A18 ORDER NUMBER AND PART MARKING MT28F004B3VG-8 B MT28F004B3VP-8 B MT28F004B3VG-8 T MT28F004B3VP-8 T MT28F004B3VG-8 BET MT28F004B3VP-8 BET MT28F004B3VG-8 TET MT28F004B3VP-8 TET 2 44-Pin SOP VPP A17 CE VSS DQ0 15 30 DQ8 ...

  • Page 3

    BYTE# I/O Control Logic Addr. A0–A17/(A18) Buffer/ Latch A9 Power (Current) Control WP# CE# Command OE# Execution WE# Logic RP NOTE: 1. Does not apply to MT28F004B3. Figure 2: Functional Block Diagram 16KB Boot Block ...

  • Page 4

    ... SMART 3 BOOT BLOCK FLASH MEMORY SYMBOL TYPE WE# Input Write Enable: Determines if a given cycle is a WRITE cycle. If WE# is LOW, the cycle is either a WRITE to the command execution logic (CEL the memory array. WP# Input Write Protect: Unlocks the boot block when HIGH (3.3V) or PPH 1 WRITE or ERASE ...

  • Page 5

    ... The READ ARRAY command must be issued before reading the array after writing or erasing. 6. When WP RP# may 12V 12V; may also be read by issuing the IDENTIFY DEVICE command A1–A8, A10–A17 = 10. Value reflects DQ8–DQ15. 09005aef8114a789 F45.fm - Rev. E 6/04 EN SMART 3 BOOT BLOCK FLASH MEMORY 1 CE# OE# WE# WP# BYTE ...

  • Page 6

    ... Operation must be preceded by WRITE SETUP command. 5. The READ ARRAY command must be issued before reading the array after writing or erasing When WP RP# may 12V 12V; may also be read by issuing the IDENTIFY DEVICE command A1–A8, A10–A18 = 09005aef8114a789 F45.fm - Rev. E 6/04 EN SMART 3 BOOT BLOCK FLASH MEMORY 1 RP# CE# OE# WE ...

  • Page 7

    ... The MT28F400B3 allows selection of an 8-bit (512K 16-bit (256K x 16) data bus for reading and writ- ing the memory. The BYTE# pin is used to select the bus width. In the x16 configuration, control data is read or written only on the lower eight bits (DQ0– ...

  • Page 8

    ... Command Execution Logic (CEL) The CEL receives and interprets commands to the device. These commands control the operation of the ISM and the read path (i.e., memory array, ID register or status register). Commands may be issued to the CEL while the ISM is active. However, there are restric- tions on ...

  • Page 9

    ... When the memory array is accessed as a 256K x 16, BYTE# is HIGH, and data is output on DQ0–DQ15. To access the memory array as a 512K x 8, BYTE# must be LOW, DQ8–DQ14 must be High-Z, and all data must be output on DQ0–DQ7. The DQ15/A-1 pin becomes the lowest order address input so that 524,288 locations can be read ...

  • Page 10

    ... CEL. A command input issues an 8-bit command to the CEL to control the mode of operation of the device. A WRITE is used to input data to the memory array. The following sec- tion describes both types of inputs. More information describing how to use the two types of inputs to write or erase the device is provided in the Command Execu- tion section ...

  • Page 11

    ... SR0-2 RESERVED 09005aef8114a789 F45.fm - Rev. E 6/04 EN SMART 3 BOOT BLOCK FLASH MEMORY All of the defined bits are set by the ISM, but only the ISM and erase suspend status bits are reset by the ISM. The erase, write and V cleared using CLEAR STATUS REGISTER. If the V ...

  • Page 12

    ... Addresses are “Don’t Care” in first cycle but must be held stable Address to be written Data to be written to WA. 09005aef8114a789 F45.fm - Rev. E 6/04 EN SMART 3 BOOT BLOCK FLASH MEMORY the write address and data are issued and V brought to V requires that the RP# pin be brought to V ...

  • Page 13

    ... NOTE: 1. SR3–SR5 must be cleared using CLEAR STATUS REGISTER. 09005aef8114a789 F45.fm - Rev. E 6/04 EN SMART 3 BOOT BLOCK FLASH MEMORY ERASE Suspension The only command that may be issued while an ERASE is in progress is ERASE SUSPEND. This com- mand enables other commands to be executed while pausing the ERASE in progress ...

  • Page 14

    ... ISM continues to operate, and the device consumes the respective active power until the WRITE or ERASE is completed. 09005aef8114a789 F45.fm - Rev. E 6/04 EN SMART 3 BOOT BLOCK FLASH MEMORY Power-Up The likelihood of unwanted WRITE or ERASE opera- tions is minimized because two consecutive cycles are required to execute either operation. However, to reset ...

  • Page 15

    ... If SR3 is set during a WRITE or BLOCK ERASE attempt, CLEAR STATUS REGISTER must be issued before further WRITE or ERASE operations are allowed by the CEL. 5. Status register bits 3-5 must be cleared using CLEAR STATUS REGISTER. 09005aef8114a789 F45.fm - Rev. E 6/04 EN SMART 3 BOOT BLOCK FLASH MEMORY 1 Start (WRITE completed Micron Technology, Inc ...

  • Page 16

    ... If SR3 is set during a WRITE or BLOCK ERASE attempt, CLEAR STATUS REGISTER must be issued before further WRITE or ERASE operations are allowed by the CEL. 5. Status register bits 3-5 must be cleared using CLEAR STATUS REGISTER. 09005aef8114a789 F45.fm - Rev. E 6/04 EN SMART 3 BOOT BLOCK FLASH MEMORY Figure 8: Complete BLOCK ERASE 1 Start (ERASE completed) NO ...

  • Page 17

    ... Figure 9: ERASE SUSPEND/RESUME Sequence 09005aef8114a789 F45.fm - Rev. E 6/04 EN SMART 3 BOOT BLOCK FLASH MEMORY Start (ERASE in progress) WRITE B0h (ERASE SUSPEND 3. STATUS REGISTER READ NO SR7 = 1? YES NO SR6 = 1? YES WRITE FFh (READ ARRAY) Done NO Reading? YES WRITE D0h (ERASE RESUME) Resume ERASE 17 ERASE Completed Micron Technology, Inc., reserves the right to change products or specifications without notice. © ...

  • Page 18

    ... All voltages referenced 09005aef8114a789 F45.fm - Rev. E 6/04 EN SMART 3 BOOT BLOCK FLASH MEMORY *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other condi- † ...

  • Page 19

    ... DEEP POWER-DOWN CURRENT: PP NOTE: 1. Vcc = MAX Vcc during I tests dependent on cycle rates dependent on output loading. Specified values are obtained with the outputs open. CC 09005aef8114a789 F45.fm - Rev. E 6/04 EN SMART 3 BOOT BLOCK FLASH MEMORY SYMBOL 1 ≤ +70°C) and Extended Temperature (-40°C ≤ T SYMBOL - 0.2V 0.2V ...

  • Page 20

    ... Input pulse levels Input rise and fall times . . . . . . . . . . . . . . . . . . . . . . .<10ns Input timing reference level . . . . . . . . . . . . . . . . . . . . 1.5V Output timing reference level 1.5V Output load 1TTL gate and CL = 50pF 09005aef8114a789 F45.fm - Rev. E 6/04 EN SMART 3 BOOT BLOCK FLASH MEMORY 1 ≤ +70°C) and Extended Temperature (-40°C ≤ T SYMBOL ...

  • Page 21

    ... Commercial Temperature (0ºC ≤ Extended Temperature (-40ºC ≤ -8/-8 ET SYMBOL MIN MAX ACE t AOE t AA NOTE: 1. BYTE# = HIGH (MT28F400B3 only). 09005aef8114a789 F45.fm - Rev. E 6/04 EN SMART 3 BOOT BLOCK FLASH MEMORY Figure 10: Word-Wide READ Cycle ACE t AOE t RWH ≤ +70ºC) ≤ +85ºC) UNITS SYMBOL t ns RWH ...

  • Page 22

    ... A -8/-8 ET SYMBOL MIN MAX ACE t AOE t AA NOTE: 1. BYTE# = LOW (MT28F400B3 only). 09005aef8114a789 F45.fm - Rev. E 6/04 EN SMART 3 BOOT BLOCK FLASH MEMORY Figure 11: Byte-Wide READ Cycle VALID ADDRESS ACE t AOE HIGH-Z t RWH ≤ +70°C) ≤ +85°C) UNITS SYMBOL t ns RWH t 80 ...

  • Page 23

    ... Applies to MT28F004B3 and MT28F400B3 with BYTE = LOW. 8. Parameter is specified when device is not accessed. Actual current draw will executed while the device is in erase suspend mode. 09005aef8114a789 F45.fm - Rev. E 6/04 EN SMART 3 BOOT BLOCK FLASH MEMORY ≤ +70°C) and Extended Temperature (-40°C ≤ T SYMBOL V PPLK ...

  • Page 24

    ... REL is required to relock boot block after WRITE or ERASE to boot block. 7. Typical values measured +25º Assumes no system overhead. 9. Typical WRITE times use checkerboard data pattern. 09005aef8114a789 F45.fm - Rev. E 6/04 EN SMART 3 BOOT BLOCK FLASH MEMORY ≤ +70°C) and Extended Temperature (-40°C ≤ T SYMBOL WPH ( ...

  • Page 25

    ... Address inputs are “Don’t Care” but must be held stable BYTE# is LOW, data and command are 8-bit. If BYTE# is HIGH, data is 16-bit and command is 8-bit (MT28F400B3 only Either RP WP# HIGH unlocks the boot block. HH 09005aef8114a789 F45.fm - Rev. E 6/04 EN SMART 3 BOOT BLOCK FLASH MEMORY Figure 12: WRITE/ERASE Cycle WE#-Controlled WRITE/ERASE Note ...

  • Page 26

    ... Address inputs are “Don’t Care” but must be held stable BYTE# is LOW, data and command are 8-bit. If BYTE# is HIGH, data is 16-bit and command is 8-bit (MT28F400B3 only Either RP WP# HIGH unlocks the boot block. HH 09005aef8114a789 F45.fm - Rev. E 6/04 EN SMART 3 BOOT BLOCK FLASH MEMORY Figure 13: WRITE/ERASE Cycle CE#-Controlled WRITE/ERASE Note ...

  • Page 27

    ... NOTE: 1. All dimensions in millimeters. 2. Package width and length do not include mold protrusion; allowable mold protrusion is .01” per side. 09005aef8114a789 F45.fm - Rev. E 6/04 EN SMART 3 BOOT BLOCK FLASH MEMORY Figure 14: 40-Pin Plastic TSOP I (10mm x 20mm) 0.25 FOR REFERENCE ONLY 1.20 MAX SEE DETAIL A Micron Technology, Inc ...

  • Page 28

    ... NOTE: 1. All dimensions in millimeters. 2. Package width and length do not include mold protrusion; allowable mold protrusion is .01” per side. 09005aef8114a789 F45.fm - Rev. E 6/04 EN SMART 3 BOOT BLOCK FLASH MEMORY Figure 15: 48-Pin Plastic TSOP I (12mm x 20mm) 20.00 ±0.25 18.40 ±0.08 SEE DETAIL A 1 ...

  • Page 29

    ... E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. 09005aef8114a789 F45.fm - Rev. E 6/04 EN SMART 3 BOOT BLOCK FLASH MEMORY Figure 16: 44-Pin Plastic SOP1 (500 mil) +0.05 0.45 (TYP) -0 ...

  • Page 30

    ... MT28F004B3 only available in VG package • Added 80ns access time for commercial and extended temperature ranges 09005aef8114a789 F45.fm - Rev. E 6/04 EN SMART 3 BOOT BLOCK FLASH MEMORY Micron Technology, Inc., reserves the right to change products or specifications without notice. 30 4Mb ©2003 Micron Technology, Inc. All rights reserved. ...