MT28F004B3VG-8 BET TR Micron Technology Inc, MT28F004B3VG-8 BET TR Datasheet - Page 11

• Manufacturer Part Number: MT28F004B3VG-8 BET TR
• Description: IC FLASH 4MBIT 80NS 40TSOP
• Manufacturer: Micron Technology Inc

Specifications of MT28F004B3VG-8 BET TR

• Format - Memory: FLASH
• Memory Type: FLASH - Nor
• Memory Size: 4M (512K x 8)
• Speed: 80ns
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-TSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

ISM Status Register
to check for WRITE or ERASE completion or any
related errors. During or following a WRITE, ERASE or
ERASE SUSPEND, a READ operation outputs the status
register contents on DQ0–DQ7 without prior com-
mand. While the status register contents are read, the
outputs are not updated if there is a change in the ISM
status unless OE# or CE# is toggled. If the device is not
in the write, erase, erase suspend or status register read
mode, READ STATUS REGISTER (70h) can be issued to
view the status register contents.
Table 5:
09005aef8114a789
F45.fm - Rev. E 6/04 EN
STATUS BIT #
The 8-bit ISM status register (see Table 2) is polled
SR0-2
SR7
SR6
SR5
SR4
SR3
ISMS
7
Status Register Bit Definitions
ISM STATUS (ISMS)
1 = Ready
0 = Busy
ERASE SUSPEND STATUS (ESS)
1 = ERASE suspended
0 = ERASE in progress/completed
ERASE STATUS (ES)
1 = BLOCK ERASE error
0 = Successful BLOCK ERASE
WRITE STATUS (WS)
1 = WORD/BYTE WRITE error
0 = Successful WORD/BYTE WRITE
V
1 = No V
0 = V
RESERVED
PP
STATUS (V
PP
STATUS REGISTER BIT
present
PP
voltage detected
ESS
6
PP
S)
ES
5
DESCRIPTION
The ISMS bit displays the active status of the state machine during
WRITE or BLOCK ERASE operations. The controlling logic polls this bit
to determine when the erase and write status bits are valid.
Issuing an ERASE SUSPEND places the ISM in the suspend mode and
sets this and the ISMS bit to “1.” The ESS bit remains “1” until an
ERASE RESUME is issued.
ES is set to “1” after the maximum number of ERASE cycles is
executed by the ISM without a successful verify. ES is only cleared by a
CLEAR STATUS REGISTER command or after a RESET.
WS is set to “1” after the maximum number of WRITE cycles is
executed by the ISM without a successful verify. WS is only cleared by
a CLEAR STATUS REGISTER command or after a RESET.
V
V
pin is
V
Reserved for future use.
SMART 3 BOOT BLOCK FLASH MEMORY
PP
PP
PP
S detects the presence of a V
S must be cleared by CLEAR STATUS REGISTER or by a RESET.
continuously, nor does it indicate a valid V
sampled for 3.3V or 5V after WRITE or ERASE CONFIRM is given.
11
the ISM and erase suspend status bits are reset by the
ISM. The erase, write and V
cleared using CLEAR STATUS REGISTER. If the V
status bit (SR3) is set, the CEL does not allow further
WRITE or ERASE operations until the status register is
cleared. This enables the user to choose when to poll
and clear the status register. For example, the host sys-
tem may perform multiple BYTE WRITE operations
before checking the status register instead of checking
after each individual WRITE. Asserting the RP# signal
or powering down the device also clears the status reg-
ister.
All of the defined bits are set by the ISM, but only
WS
Micron Technology, Inc., reserves the right to change products or specifications without notice.
4
PP
voltage. It does not monitor
V
PP
3
S
©2003 Micron Technology, Inc. All rights reserved.
PP
status bits must be
PP
voltage. The V
2–0
R
4Mb
PP
PP